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authorYong Li <yong.li@intel.com>2023-04-20 12:36:40 +0800
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>2023-06-06 20:37:18 +0000
commitded0b489af09cde5afa05d74acdb12cd4b4f8394 (patch)
tree8c7d57f12a2c40bf3f30f7050fbf15521bb067ae /MdePkg
parentd189de3b0a2f44f4c9b87ed120be16569ea19b51 (diff)
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MdePkg/BaseLib: Add SpeculationBarrier implementation for RiscV64
Implement the SpeculationBarrier with implementations consisting of fence instruction which provides finer-grain memory orderings. Perform Data Barrier in RiscV: fence rw,rw Perform Instruction Barrier in RiscV: fence.i; fence r,r More detail is in Appendix A: RVWMO Explanatory Material in https://github.com/riscv/riscv-isa-manual This API is first introduced in the below commits for IA32 and x64 https://github.com/tianocore/edk2/commit/d9f1cac51bd354507e880e614d11a1dc160d38a3 https://github.com/tianocore/edk2/commit/e83d841fdc2878959185c4c6cc38a7a1e88377a4 and below the commit for ARM and AArch64 implementation https://github.com/tianocore/edk2/commit/c0959b4426b2da45cdb8146a5116bb4fd9b86534 This commit is to add the RiscV64 implementation which will be used by variable service under Variable/RuntimeDxe Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Evan Chai <evan.chai@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Tuan Phan <tphan@ventanamicro.com> Signed-off-by: Yong Li <yong.li@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Diffstat (limited to 'MdePkg')
-rw-r--r--MdePkg/Library/BaseLib/BaseLib.inf1
-rw-r--r--MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S34
2 files changed, 35 insertions, 0 deletions
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 3a48492b1a..03c7b02e82 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -404,6 +404,7 @@
RiscV64/CpuScratch.S | GCC
RiscV64/ReadTimer.S | GCC
RiscV64/RiscVMmu.S | GCC
+ RiscV64/SpeculationBarrier.S | GCC
[Sources.LOONGARCH64]
Math64.c
diff --git a/MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S b/MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S
new file mode 100644
index 0000000000..581a765399
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S
@@ -0,0 +1,34 @@
+##------------------------------------------------------------------------------
+#
+# SpeculationBarrier() for RISCV64
+#
+# Copyright (c) 2023, Intel Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##------------------------------------------------------------------------------
+
+.text
+.p2align 2
+
+ASM_GLOBAL ASM_PFX(SpeculationBarrier)
+
+
+#/**
+# Uses as a barrier to stop speculative execution.
+#
+# Ensures that no later instruction will execute speculatively, until all prior
+# instructions have completed.
+#
+#**/
+#VOID
+#EFIAPI
+#SpeculationBarrier (
+# VOID
+# );
+#
+ASM_PFX(SpeculationBarrier):
+ fence rw,rw
+ fence.i
+ fence r,r
+ ret