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authorLaszlo Ersek <lersek@redhat.com>2018-03-01 18:55:09 +0100
committerLaszlo Ersek <lersek@redhat.com>2018-03-06 13:30:14 +0100
commitb1bfdd65970bc4744b7abe644d5849c1dceb50ce (patch)
tree26cbabc2c9f53179e8c373e08ff61f76bf88c021 /OvmfPkg/Library/SmmCpuFeaturesLib
parent6d576e7ac430bf7aa68efef55bd2e07908633462 (diff)
downloadedk2-b1bfdd65970bc4744b7abe644d5849c1dceb50ce.tar.gz
edk2-b1bfdd65970bc4744b7abe644d5849c1dceb50ce.tar.bz2
edk2-b1bfdd65970bc4744b7abe644d5849c1dceb50ce.zip
OvmfPkg/SmmCpuFeaturesLib: rewrap to 79 columns
There are many overlong lines; it's hard to work with the library like this. Rewrap all files to 79 columns. ( The rewrapping of the "mSmmCpuRegisterRanges" and "mSmmCpuWidthOffset" arrays was verified by hexdumping the arrays in SmmCpuFeaturesLibConstructor(), both before and after the patch, and comparing the dumps. Contents of "mSmmCpuRegisterRanges", IA32 build: > mSmmCpuRegisterRanges: { > mSmmCpuRegisterRanges: 000000 04 00 00 00 0A 00 00 00 07 00 00 00 14 00 00 00 > mSmmCpuRegisterRanges: 000010 2E 00 00 00 1B 00 00 00 33 00 00 00 36 00 00 00 > mSmmCpuRegisterRanges: 000020 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > mSmmCpuRegisterRanges: } Contents of "mSmmCpuRegisterRanges", X64 build: > mSmmCpuRegisterRanges: { > mSmmCpuRegisterRanges: 000000 04 00 00 00 0A 00 00 00 07 00 00 00 00 00 00 00 > mSmmCpuRegisterRanges: 000010 14 00 00 00 2E 00 00 00 1B 00 00 00 00 00 00 00 > mSmmCpuRegisterRanges: 000020 33 00 00 00 36 00 00 00 04 00 00 00 00 00 00 00 > mSmmCpuRegisterRanges: 000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > mSmmCpuRegisterRanges: } Contents of "mSmmCpuWidthOffset", both IA32 and X64 builds: > mSmmCpuWidthOffset: { > mSmmCpuWidthOffset: 000000 00 00 00 00 00 00 00 00 00 00 00 08 00 00 68 02 > mSmmCpuWidthOffset: 000010 6C 02 00 00 00 08 00 00 88 02 8C 02 00 00 00 08 > mSmmCpuWidthOffset: 000020 00 00 78 02 7C 02 00 00 00 00 00 00 64 02 68 02 > mSmmCpuWidthOffset: 000030 00 00 00 00 00 00 84 02 88 02 00 00 00 00 00 00 > mSmmCpuWidthOffset: 000040 74 02 78 02 00 00 00 00 00 00 00 00 04 00 00 00 > mSmmCpuWidthOffset: 000050 04 04 A8 03 00 02 00 00 00 00 04 04 AC 03 10 02 > mSmmCpuWidthOffset: 000060 00 00 00 00 04 04 B0 03 20 02 00 00 00 00 04 04 > mSmmCpuWidthOffset: 000070 B4 03 30 02 00 00 00 00 04 04 B8 03 40 02 00 00 > mSmmCpuWidthOffset: 000080 00 00 04 04 BC 03 50 02 00 00 00 00 00 04 00 00 > mSmmCpuWidthOffset: 000090 70 02 00 00 00 00 04 04 C4 03 90 02 00 00 00 00 > mSmmCpuWidthOffset: 0000A0 04 08 C8 03 60 03 64 03 00 00 04 08 CC 03 68 03 > mSmmCpuWidthOffset: 0000B0 6C 03 00 00 00 08 00 00 B8 03 BC 03 01 00 00 08 > mSmmCpuWidthOffset: 0000C0 00 00 B0 03 B4 03 01 00 00 08 00 00 A8 03 AC 03 > mSmmCpuWidthOffset: 0000D0 01 00 00 08 00 00 A0 03 A4 03 01 00 00 08 00 00 > mSmmCpuWidthOffset: 0000E0 98 03 9C 03 01 00 00 08 00 00 90 03 94 03 01 00 > mSmmCpuWidthOffset: 0000F0 00 08 00 00 88 03 8C 03 01 00 00 08 00 00 80 03 > mSmmCpuWidthOffset: 000100 84 03 01 00 04 08 D0 03 F8 03 FC 03 01 00 04 08 > mSmmCpuWidthOffset: 000110 DC 03 E0 03 E4 03 01 00 04 08 D4 03 F0 03 F4 03 > mSmmCpuWidthOffset: 000120 01 00 04 08 D8 03 E8 03 EC 03 01 00 04 08 E0 03 > mSmmCpuWidthOffset: 000130 D8 03 DC 03 01 00 04 08 E4 03 D0 03 D4 03 01 00 > mSmmCpuWidthOffset: 000140 04 08 E8 03 C8 03 CC 03 01 00 04 08 EC 03 C0 03 > mSmmCpuWidthOffset: 000150 C4 03 01 00 04 08 F0 03 78 03 7C 03 01 00 04 08 > mSmmCpuWidthOffset: 000160 F4 03 70 03 74 03 01 00 04 08 FC 03 58 03 5C 03 > mSmmCpuWidthOffset: 000170 00 00 04 08 F8 03 50 03 54 03 00 00 00 04 00 00 > mSmmCpuWidthOffset: 000180 48 03 4C 03 00 00 > mSmmCpuWidthOffset: } ) Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Brijesh Singh <brijesh.singh@amd.com> Reviewed-by: Brijesh Singh <brijesh.singh@amd.com>
Diffstat (limited to 'OvmfPkg/Library/SmmCpuFeaturesLib')
-rw-r--r--OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c594
-rw-r--r--OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf10
2 files changed, 489 insertions, 115 deletions
diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
index a307f64c9c..a876a6e347 100644
--- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
+++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
@@ -1,15 +1,15 @@
/** @file
-The CPU specific programming for PiSmmCpuDxeSmm module.
+ The CPU specific programming for PiSmmCpuDxeSmm module.
-Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
+ Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <PiSmm.h>
@@ -87,7 +87,10 @@ SmmCpuFeaturesInitializeProcessor (
//
// Configure SMBASE.
//
- CpuState = (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
+ CpuState = (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)(
+ SMM_DEFAULT_SMBASE +
+ SMRAM_SAVE_STATE_MAP_OFFSET
+ );
if ((CpuState->x86.SMMRevId & 0xFFFF) == 0) {
CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
} else {
@@ -117,8 +120,8 @@ SmmCpuFeaturesInitializeProcessor (
@param[in] CpuIndex The index of the CPU to hook. The value
must be between 0 and the NumberOfCpus
- field in the System Management System Table
- (SMST).
+ field in the System Management System
+ Table (SMST).
@param[in] CpuState Pointer to SMRAM Save State Map for the
currently executing CPU.
@param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
@@ -140,8 +143,9 @@ SmmCpuFeaturesHookReturnFromSmm (
)
{
UINT64 OriginalInstructionPointer;
- QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)CpuState;
+ QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
+ CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)CpuState;
if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
OriginalInstructionPointer = (UINT64)CpuSaveState->x86._EIP;
CpuSaveState->x86._EIP = (UINT32)NewInstructionPointer;
@@ -191,9 +195,10 @@ SmmCpuFeaturesSmmRelocationComplete (
and the default SMI handler must be used.
@retval 0 Use the default SMI handler.
- @retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()
- The caller is required to allocate enough SMRAM for each CPU to
- support the size of the custom SMI handler.
+ @retval > 0 Use the SMI handler installed by
+ SmmCpuFeaturesInstallSmiHandler(). The caller is required to
+ allocate enough SMRAM for each CPU to support the size of the
+ custom SMI handler.
**/
UINTN
EFIAPI
@@ -205,10 +210,10 @@ SmmCpuFeaturesGetSmiHandlerSize (
}
/**
- Install a custom SMI handler for the CPU specified by CpuIndex. This function
- is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater
- than zero and is called by the CPU that was elected as monarch during System
- Management Mode initialization.
+ Install a custom SMI handler for the CPU specified by CpuIndex. This
+ function is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size
+ is greater than zero and is called by the CPU that was elected as monarch
+ during System Management Mode initialization.
@param[in] CpuIndex The index of the CPU to install the custom SMI handler.
The value must be between 0 and the NumberOfCpus field
@@ -263,8 +268,8 @@ SmmCpuFeaturesNeedConfigureMtrrs (
}
/**
- Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
- returns TRUE.
+ Disable SMRR register if SMRR is supported and
+ SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.
**/
VOID
EFIAPI
@@ -278,8 +283,8 @@ SmmCpuFeaturesDisableSmrr (
}
/**
- Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
- returns TRUE.
+ Enable SMRR register if SMRR is supported and
+ SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.
**/
VOID
EFIAPI
@@ -313,9 +318,9 @@ SmmCpuFeaturesRendezvousEntry (
/**
Processor specific hook point each time a CPU exits System Management Mode.
- @param[in] CpuIndex The index of the CPU that is exiting SMM. The value must
- be between 0 and the NumberOfCpus field in the System
- Management System Table (SMST).
+ @param[in] CpuIndex The index of the CPU that is exiting SMM. The value
+ must be between 0 and the NumberOfCpus field in the
+ System Management System Table (SMST).
**/
VOID
EFIAPI
@@ -399,12 +404,14 @@ SmmCpuFeaturesSetSmmRegister (
}
///
-/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
+/// Macro used to simplify the lookup table entries of type
+/// CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
///
#define SMM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field)
///
-/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_REGISTER_RANGE
+/// Macro used to simplify the lookup table entries of type
+/// CPU_SMM_SAVE_STATE_REGISTER_RANGE
///
#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }
@@ -434,66 +441,383 @@ typedef struct {
} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;
///
-/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER
+/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER
/// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
///
static CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {
- SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO),
- SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_STATE_REGISTER_RIP),
- SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_STATE_REGISTER_CR4),
+ SMM_REGISTER_RANGE (
+ EFI_SMM_SAVE_STATE_REGISTER_GDTBASE,
+ EFI_SMM_SAVE_STATE_REGISTER_LDTINFO
+ ),
+ SMM_REGISTER_RANGE (
+ EFI_SMM_SAVE_STATE_REGISTER_ES,
+ EFI_SMM_SAVE_STATE_REGISTER_RIP
+ ),
+ SMM_REGISTER_RANGE (
+ EFI_SMM_SAVE_STATE_REGISTER_RFLAGS,
+ EFI_SMM_SAVE_STATE_REGISTER_CR4
+ ),
{ (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }
};
///
-/// Lookup table used to retrieve the widths and offsets associated with each
-/// supported EFI_SMM_SAVE_STATE_REGISTER value
+/// Lookup table used to retrieve the widths and offsets associated with each
+/// supported EFI_SMM_SAVE_STATE_REGISTER value
///
static CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {
- {0, 0, 0, 0, 0, FALSE}, // Reserved
+ {
+ 0, // Width32
+ 0, // Width64
+ 0, // Offset32
+ 0, // Offset64Lo
+ 0, // Offset64Hi
+ FALSE // Writeable
+ }, // Reserved
//
// CPU Save State registers defined in PI SMM CPU Protocol.
//
- {0, 8, 0 , SMM_CPU_OFFSET (x64._GDTRBase) , SMM_CPU_OFFSET (x64._GDTRBase) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4
- {0, 8, 0 , SMM_CPU_OFFSET (x64._IDTRBase) , SMM_CPU_OFFSET (x64._IDTRBase) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5
- {0, 8, 0 , SMM_CPU_OFFSET (x64._LDTRBase) , SMM_CPU_OFFSET (x64._LDTRBase) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6
- {0, 0, 0 , SMM_CPU_OFFSET (x64._GDTRLimit), SMM_CPU_OFFSET (x64._GDTRLimit) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
- {0, 0, 0 , SMM_CPU_OFFSET (x64._IDTRLimit), SMM_CPU_OFFSET (x64._IDTRLimit) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
- {0, 0, 0 , SMM_CPU_OFFSET (x64._LDTRLimit), SMM_CPU_OFFSET (x64._LDTRLimit) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
- {0, 0, 0 , 0 , 0 + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10
-
- {4, 4, SMM_CPU_OFFSET (x86._ES) , SMM_CPU_OFFSET (x64._ES) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20
- {4, 4, SMM_CPU_OFFSET (x86._CS) , SMM_CPU_OFFSET (x64._CS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21
- {4, 4, SMM_CPU_OFFSET (x86._SS) , SMM_CPU_OFFSET (x64._SS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22
- {4, 4, SMM_CPU_OFFSET (x86._DS) , SMM_CPU_OFFSET (x64._DS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23
- {4, 4, SMM_CPU_OFFSET (x86._FS) , SMM_CPU_OFFSET (x64._FS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24
- {4, 4, SMM_CPU_OFFSET (x86._GS) , SMM_CPU_OFFSET (x64._GS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25
- {0, 4, 0 , SMM_CPU_OFFSET (x64._LDTR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26
- {4, 4, SMM_CPU_OFFSET (x86._TR) , SMM_CPU_OFFSET (x64._TR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27
- {4, 8, SMM_CPU_OFFSET (x86._DR7) , SMM_CPU_OFFSET (x64._DR7) , SMM_CPU_OFFSET (x64._DR7) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28
- {4, 8, SMM_CPU_OFFSET (x86._DR6) , SMM_CPU_OFFSET (x64._DR6) , SMM_CPU_OFFSET (x64._DR6) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R8) , SMM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R9) , SMM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R10) , SMM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R11) , SMM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R12) , SMM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R13) , SMM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R14) , SMM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R15) , SMM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37
- {4, 8, SMM_CPU_OFFSET (x86._EAX) , SMM_CPU_OFFSET (x64._RAX) , SMM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38
- {4, 8, SMM_CPU_OFFSET (x86._EBX) , SMM_CPU_OFFSET (x64._RBX) , SMM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39
- {4, 8, SMM_CPU_OFFSET (x86._ECX) , SMM_CPU_OFFSET (x64._RCX) , SMM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40
- {4, 8, SMM_CPU_OFFSET (x86._EDX) , SMM_CPU_OFFSET (x64._RDX) , SMM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41
- {4, 8, SMM_CPU_OFFSET (x86._ESP) , SMM_CPU_OFFSET (x64._RSP) , SMM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42
- {4, 8, SMM_CPU_OFFSET (x86._EBP) , SMM_CPU_OFFSET (x64._RBP) , SMM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43
- {4, 8, SMM_CPU_OFFSET (x86._ESI) , SMM_CPU_OFFSET (x64._RSI) , SMM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44
- {4, 8, SMM_CPU_OFFSET (x86._EDI) , SMM_CPU_OFFSET (x64._RDI) , SMM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45
- {4, 8, SMM_CPU_OFFSET (x86._EIP) , SMM_CPU_OFFSET (x64._RIP) , SMM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46
-
- {4, 8, SMM_CPU_OFFSET (x86._EFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51
- {4, 8, SMM_CPU_OFFSET (x86._CR0) , SMM_CPU_OFFSET (x64._CR0) , SMM_CPU_OFFSET (x64._CR0) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52
- {4, 8, SMM_CPU_OFFSET (x86._CR3) , SMM_CPU_OFFSET (x64._CR3) , SMM_CPU_OFFSET (x64._CR3) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53
- {0, 4, 0 , SMM_CPU_OFFSET (x64._CR4) , SMM_CPU_OFFSET (x64._CR4) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54
+ {
+ 0, // Width32
+ 8, // Width64
+ 0, // Offset32
+ SMM_CPU_OFFSET (x64._GDTRBase), // Offset64Lo
+ SMM_CPU_OFFSET (x64._GDTRBase) + 4, // Offset64Hi
+ FALSE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4
+
+ {
+ 0, // Width32
+ 8, // Width64
+ 0, // Offset32
+ SMM_CPU_OFFSET (x64._IDTRBase), // Offset64Lo
+ SMM_CPU_OFFSET (x64._IDTRBase) + 4, // Offset64Hi
+ FALSE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5
+
+ {
+ 0, // Width32
+ 8, // Width64
+ 0, // Offset32
+ SMM_CPU_OFFSET (x64._LDTRBase), // Offset64Lo
+ SMM_CPU_OFFSET (x64._LDTRBase) + 4, // Offset64Hi
+ FALSE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6
+
+ {
+ 0, // Width32
+ 0, // Width64
+ 0, // Offset32
+ SMM_CPU_OFFSET (x64._GDTRLimit), // Offset64Lo
+ SMM_CPU_OFFSET (x64._GDTRLimit) + 4, // Offset64Hi
+ FALSE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
+
+ {
+ 0, // Width32
+ 0, // Width64
+ 0, // Offset32
+ SMM_CPU_OFFSET (x64._IDTRLimit), // Offset64Lo
+ SMM_CPU_OFFSET (x64._IDTRLimit) + 4, // Offset64Hi
+ FALSE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
+
+ {
+ 0, // Width32
+ 0, // Width64
+ 0, // Offset32
+ SMM_CPU_OFFSET (x64._LDTRLimit), // Offset64Lo
+ SMM_CPU_OFFSET (x64._LDTRLimit) + 4, // Offset64Hi
+ FALSE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
+
+ {
+ 0, // Width32
+ 0, // Width64
+ 0, // Offset32
+ 0, // Offset64Lo
+ 0 + 4, // Offset64Hi
+ FALSE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10
+
+ {
+ 4, // Width32
+ 4, // Width64
+ SMM_CPU_OFFSET (x86._ES), // Offset32
+ SMM_CPU_OFFSET (x64._ES), // Offset64Lo
+ 0, // Offset64Hi
+ FALSE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20
+
+ {
+ 4, // Width32
+ 4, // Width64
+ SMM_CPU_OFFSET (x86._CS), // Offset32
+ SMM_CPU_OFFSET (x64._CS), // Offset64Lo
+ 0, // Offset64Hi
+ FALSE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21
+
+ {
+ 4, // Width32
+ 4, // Width64
+ SMM_CPU_OFFSET (x86._SS), // Offset32
+ SMM_CPU_OFFSET (x64._SS), // Offset64Lo
+ 0, // Offset64Hi
+ FALSE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22
+
+ {
+ 4, // Width32
+ 4, // Width64
+ SMM_CPU_OFFSET (x86._DS), // Offset32
+ SMM_CPU_OFFSET (x64._DS), // Offset64Lo
+ 0, // Offset64Hi
+ FALSE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23
+
+ {
+ 4, // Width32
+ 4, // Width64
+ SMM_CPU_OFFSET (x86._FS), // Offset32
+ SMM_CPU_OFFSET (x64._FS), // Offset64Lo
+ 0, // Offset64Hi
+ FALSE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24
+
+ {
+ 4, // Width32
+ 4, // Width64
+ SMM_CPU_OFFSET (x86._GS), // Offset32
+ SMM_CPU_OFFSET (x64._GS), // Offset64Lo
+ 0, // Offset64Hi
+ FALSE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25
+
+ {
+ 0, // Width32
+ 4, // Width64
+ 0, // Offset32
+ SMM_CPU_OFFSET (x64._LDTR), // Offset64Lo
+ 0, // Offset64Hi
+ FALSE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26
+
+ {
+ 4, // Width32
+ 4, // Width64
+ SMM_CPU_OFFSET (x86._TR), // Offset32
+ SMM_CPU_OFFSET (x64._TR), // Offset64Lo
+ 0, // Offset64Hi
+ FALSE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27
+
+ {
+ 4, // Width32
+ 8, // Width64
+ SMM_CPU_OFFSET (x86._DR7), // Offset32
+ SMM_CPU_OFFSET (x64._DR7), // Offset64Lo
+ SMM_CPU_OFFSET (x64._DR7) + 4, // Offset64Hi
+ FALSE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28
+
+ {
+ 4, // Width32
+ 8, // Width64
+ SMM_CPU_OFFSET (x86._DR6), // Offset32
+ SMM_CPU_OFFSET (x64._DR6), // Offset64Lo
+ SMM_CPU_OFFSET (x64._DR6) + 4, // Offset64Hi
+ FALSE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29
+
+ {
+ 0, // Width32
+ 8, // Width64
+ 0, // Offset32
+ SMM_CPU_OFFSET (x64._R8), // Offset64Lo
+ SMM_CPU_OFFSET (x64._R8) + 4, // Offset64Hi
+ TRUE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30
+
+ {
+ 0, // Width32
+ 8, // Width64
+ 0, // Offset32
+ SMM_CPU_OFFSET (x64._R9), // Offset64Lo
+ SMM_CPU_OFFSET (x64._R9) + 4, // Offset64Hi
+ TRUE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31
+
+ {
+ 0, // Width32
+ 8, // Width64
+ 0, // Offset32
+ SMM_CPU_OFFSET (x64._R10), // Offset64Lo
+ SMM_CPU_OFFSET (x64._R10) + 4, // Offset64Hi
+ TRUE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32
+
+ {
+ 0, // Width32
+ 8, // Width64
+ 0, // Offset32
+ SMM_CPU_OFFSET (x64._R11), // Offset64Lo
+ SMM_CPU_OFFSET (x64._R11) + 4, // Offset64Hi
+ TRUE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33
+
+ {
+ 0, // Width32
+ 8, // Width64
+ 0, // Offset32
+ SMM_CPU_OFFSET (x64._R12), // Offset64Lo
+ SMM_CPU_OFFSET (x64._R12) + 4, // Offset64Hi
+ TRUE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34
+
+ {
+ 0, // Width32
+ 8, // Width64
+ 0, // Offset32
+ SMM_CPU_OFFSET (x64._R13), // Offset64Lo
+ SMM_CPU_OFFSET (x64._R13) + 4, // Offset64Hi
+ TRUE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35
+
+ {
+ 0, // Width32
+ 8, // Width64
+ 0, // Offset32
+ SMM_CPU_OFFSET (x64._R14), // Offset64Lo
+ SMM_CPU_OFFSET (x64._R14) + 4, // Offset64Hi
+ TRUE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36
+
+ {
+ 0, // Width32
+ 8, // Width64
+ 0, // Offset32
+ SMM_CPU_OFFSET (x64._R15), // Offset64Lo
+ SMM_CPU_OFFSET (x64._R15) + 4, // Offset64Hi
+ TRUE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37
+
+ {
+ 4, // Width32
+ 8, // Width64
+ SMM_CPU_OFFSET (x86._EAX), // Offset32
+ SMM_CPU_OFFSET (x64._RAX), // Offset64Lo
+ SMM_CPU_OFFSET (x64._RAX) + 4, // Offset64Hi
+ TRUE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38
+
+ {
+ 4, // Width32
+ 8, // Width64
+ SMM_CPU_OFFSET (x86._EBX), // Offset32
+ SMM_CPU_OFFSET (x64._RBX), // Offset64Lo
+ SMM_CPU_OFFSET (x64._RBX) + 4, // Offset64Hi
+ TRUE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39
+
+ {
+ 4, // Width32
+ 8, // Width64
+ SMM_CPU_OFFSET (x86._ECX), // Offset32
+ SMM_CPU_OFFSET (x64._RCX), // Offset64Lo
+ SMM_CPU_OFFSET (x64._RCX) + 4, // Offset64Hi
+ TRUE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40
+
+ {
+ 4, // Width32
+ 8, // Width64
+ SMM_CPU_OFFSET (x86._EDX), // Offset32
+ SMM_CPU_OFFSET (x64._RDX), // Offset64Lo
+ SMM_CPU_OFFSET (x64._RDX) + 4, // Offset64Hi
+ TRUE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41
+
+ {
+ 4, // Width32
+ 8, // Width64
+ SMM_CPU_OFFSET (x86._ESP), // Offset32
+ SMM_CPU_OFFSET (x64._RSP), // Offset64Lo
+ SMM_CPU_OFFSET (x64._RSP) + 4, // Offset64Hi
+ TRUE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42
+
+ {
+ 4, // Width32
+ 8, // Width64
+ SMM_CPU_OFFSET (x86._EBP), // Offset32
+ SMM_CPU_OFFSET (x64._RBP), // Offset64Lo
+ SMM_CPU_OFFSET (x64._RBP) + 4, // Offset64Hi
+ TRUE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43
+
+ {
+ 4, // Width32
+ 8, // Width64
+ SMM_CPU_OFFSET (x86._ESI), // Offset32
+ SMM_CPU_OFFSET (x64._RSI), // Offset64Lo
+ SMM_CPU_OFFSET (x64._RSI) + 4, // Offset64Hi
+ TRUE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44
+
+ {
+ 4, // Width32
+ 8, // Width64
+ SMM_CPU_OFFSET (x86._EDI), // Offset32
+ SMM_CPU_OFFSET (x64._RDI), // Offset64Lo
+ SMM_CPU_OFFSET (x64._RDI) + 4, // Offset64Hi
+ TRUE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45
+
+ {
+ 4, // Width32
+ 8, // Width64
+ SMM_CPU_OFFSET (x86._EIP), // Offset32
+ SMM_CPU_OFFSET (x64._RIP), // Offset64Lo
+ SMM_CPU_OFFSET (x64._RIP) + 4, // Offset64Hi
+ TRUE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46
+
+ {
+ 4, // Width32
+ 8, // Width64
+ SMM_CPU_OFFSET (x86._EFLAGS), // Offset32
+ SMM_CPU_OFFSET (x64._RFLAGS), // Offset64Lo
+ SMM_CPU_OFFSET (x64._RFLAGS) + 4, // Offset64Hi
+ TRUE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51
+
+ {
+ 4, // Width32
+ 8, // Width64
+ SMM_CPU_OFFSET (x86._CR0), // Offset32
+ SMM_CPU_OFFSET (x64._CR0), // Offset64Lo
+ SMM_CPU_OFFSET (x64._CR0) + 4, // Offset64Hi
+ FALSE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52
+
+ {
+ 4, // Width32
+ 8, // Width64
+ SMM_CPU_OFFSET (x86._CR3), // Offset32
+ SMM_CPU_OFFSET (x64._CR3), // Offset64Lo
+ SMM_CPU_OFFSET (x64._CR3) + 4, // Offset64Hi
+ FALSE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53
+
+ {
+ 0, // Width32
+ 4, // Width64
+ 0, // Offset32
+ SMM_CPU_OFFSET (x64._CR4), // Offset64Lo
+ SMM_CPU_OFFSET (x64._CR4) + 4, // Offset64Hi
+ FALSE // Writeable
+ }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54
};
//
@@ -517,8 +841,11 @@ GetRegisterIndex (
UINTN Index;
UINTN Offset;
- for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_FIRST_INDEX; mSmmCpuRegisterRanges[Index].Length != 0; Index++) {
- if (Register >= mSmmCpuRegisterRanges[Index].Start && Register <= mSmmCpuRegisterRanges[Index].End) {
+ for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_FIRST_INDEX;
+ mSmmCpuRegisterRanges[Index].Length != 0;
+ Index++) {
+ if (Register >= mSmmCpuRegisterRanges[Index].Start &&
+ Register <= mSmmCpuRegisterRanges[Index].End) {
return Register - mSmmCpuRegisterRanges[Index].Start + Offset;
}
Offset += mSmmCpuRegisterRanges[Index].Length;
@@ -529,18 +856,23 @@ GetRegisterIndex (
/**
Read a CPU Save State register on the target processor.
- This function abstracts the differences that whether the CPU Save State register is in the
- IA32 CPU Save State Map or X64 CPU Save State Map.
+ This function abstracts the differences that whether the CPU Save State
+ register is in the IA32 CPU Save State Map or X64 CPU Save State Map.
- This function supports reading a CPU Save State register in SMBase relocation handler.
+ This function supports reading a CPU Save State register in SMBase relocation
+ handler.
- @param[in] CpuIndex Specifies the zero-based index of the CPU save state.
+ @param[in] CpuIndex Specifies the zero-based index of the CPU save
+ state.
@param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
- @param[in] Width The number of bytes to read from the CPU save state.
- @param[out] Buffer Upon return, this holds the CPU register value read from the save state.
+ @param[in] Width The number of bytes to read from the CPU save
+ state.
+ @param[out] Buffer Upon return, this holds the CPU register value
+ read from the save state.
@retval EFI_SUCCESS The register was read from Save State.
- @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.
+ @retval EFI_NOT_FOUND The register is not defined for the Save State
+ of Processor.
@retval EFI_INVALID_PARAMTER This or Buffer is NULL.
**/
@@ -558,14 +890,16 @@ ReadSaveStateRegisterByIndex (
if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
//
- // If 32-bit mode width is zero, then the specified register can not be accessed
+ // If 32-bit mode width is zero, then the specified register can not be
+ // accessed
//
if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
return EFI_NOT_FOUND;
}
//
- // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed
+ // If Width is bigger than the 32-bit mode width, then the specified
+ // register can not be accessed
//
if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
return EFI_INVALID_PARAMETER;
@@ -575,17 +909,23 @@ ReadSaveStateRegisterByIndex (
// Write return buffer
//
ASSERT(CpuSaveState != NULL);
- CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width);
+ CopyMem (
+ Buffer,
+ (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,
+ Width
+ );
} else {
//
- // If 64-bit mode width is zero, then the specified register can not be accessed
+ // If 64-bit mode width is zero, then the specified register can not be
+ // accessed
//
if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
return EFI_NOT_FOUND;
}
//
- // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed
+ // If Width is bigger than the 64-bit mode width, then the specified
+ // register can not be accessed
//
if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
return EFI_INVALID_PARAMETER;
@@ -594,12 +934,20 @@ ReadSaveStateRegisterByIndex (
//
// Write lower 32-bits of return buffer
//
- CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN(4, Width));
+ CopyMem (
+ Buffer,
+ (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,
+ MIN (4, Width)
+ );
if (Width >= 4) {
//
// Write upper 32-bits of return buffer
//
- CopyMem((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);
+ CopyMem (
+ (UINT8 *)Buffer + 4,
+ (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,
+ Width - 4
+ );
}
}
return EFI_SUCCESS;
@@ -620,8 +968,8 @@ ReadSaveStateRegisterByIndex (
@retval EFI_SUCCESS The register was read from Save State.
@retval EFI_INVALID_PARAMTER Buffer is NULL.
- @retval EFI_UNSUPPORTED This function does not support reading Register.
-
+ @retval EFI_UNSUPPORTED This function does not support reading
+ Register.
**/
EFI_STATUS
EFIAPI
@@ -674,7 +1022,9 @@ SmmCpuFeaturesReadSaveStateRegister (
//
RegisterIndex = GetRegisterIndex (Register);
if (RegisterIndex == 0) {
- return Register < EFI_SMM_SAVE_STATE_REGISTER_IO ? EFI_NOT_FOUND : EFI_UNSUPPORTED;
+ return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?
+ EFI_NOT_FOUND :
+ EFI_UNSUPPORTED);
}
return ReadSaveStateRegisterByIndex (CpuIndex, RegisterIndex, Width, Buffer);
@@ -694,7 +1044,8 @@ SmmCpuFeaturesReadSaveStateRegister (
@retval EFI_SUCCESS The register was written to Save State.
@retval EFI_INVALID_PARAMTER Buffer is NULL.
- @retval EFI_UNSUPPORTED This function does not support writing Register.
+ @retval EFI_UNSUPPORTED This function does not support writing
+ Register.
**/
EFI_STATUS
EFIAPI
@@ -729,14 +1080,16 @@ SmmCpuFeaturesWriteSaveStateRegister (
//
RegisterIndex = GetRegisterIndex (Register);
if (RegisterIndex == 0) {
- return Register < EFI_SMM_SAVE_STATE_REGISTER_IO ? EFI_NOT_FOUND : EFI_UNSUPPORTED;
+ return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?
+ EFI_NOT_FOUND :
+ EFI_UNSUPPORTED);
}
CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
//
// Do not write non-writable SaveState, because it will cause exception.
- //
+ //
if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {
return EFI_UNSUPPORTED;
}
@@ -746,14 +1099,16 @@ SmmCpuFeaturesWriteSaveStateRegister (
//
if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
//
- // If 32-bit mode width is zero, then the specified register can not be accessed
+ // If 32-bit mode width is zero, then the specified register can not be
+ // accessed
//
if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
return EFI_NOT_FOUND;
}
//
- // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed
+ // If Width is bigger than the 32-bit mode width, then the specified
+ // register can not be accessed
//
if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
return EFI_INVALID_PARAMETER;
@@ -762,17 +1117,23 @@ SmmCpuFeaturesWriteSaveStateRegister (
// Write SMM State register
//
ASSERT (CpuSaveState != NULL);
- CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);
+ CopyMem (
+ (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,
+ Buffer,
+ Width
+ );
} else {
//
- // If 64-bit mode width is zero, then the specified register can not be accessed
+ // If 64-bit mode width is zero, then the specified register can not be
+ // accessed
//
if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
return EFI_NOT_FOUND;
}
//
- // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed
+ // If Width is bigger than the 64-bit mode width, then the specified
+ // register can not be accessed
//
if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
return EFI_INVALID_PARAMETER;
@@ -781,12 +1142,20 @@ SmmCpuFeaturesWriteSaveStateRegister (
//
// Write lower 32-bits of SMM State register
//
- CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));
+ CopyMem (
+ (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,
+ Buffer,
+ MIN (4, Width)
+ );
if (Width >= 4) {
//
// Write upper 32-bits of SMM State register
//
- CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);
+ CopyMem (
+ (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,
+ (UINT8 *)Buffer + 4,
+ Width - 4
+ );
}
}
return EFI_SUCCESS;
@@ -805,22 +1174,25 @@ SmmCpuFeaturesCompleteSmmReadyToLock (
}
/**
- This API provides a method for a CPU to allocate a specific region for storing page tables.
+ This API provides a method for a CPU to allocate a specific region for
+ storing page tables.
This API can be called more once to allocate memory for page tables.
- Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
- allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
- is returned. If there is not enough memory remaining to satisfy the request, then NULL is
- returned.
+ Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns
+ a pointer to the allocated buffer. The buffer returned is aligned on a 4KB
+ boundary. If Pages is 0, then NULL is returned. If there is not enough
+ memory remaining to satisfy the request, then NULL is returned.
- This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.
+ This function can also return NULL if there is no preference on where the
+ page tables are allocated in SMRAM.
@param Pages The number of 4 KB pages to allocate.
@return A pointer to the allocated buffer for page tables.
@retval NULL Fail to allocate a specific region for storing page tables,
- Or there is no preference on where the page tables are allocated in SMRAM.
+ Or there is no preference on where the page tables are
+ allocated in SMRAM.
**/
VOID *
diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
index 31edf3a9c1..75b24606b9 100644
--- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
+++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
@@ -2,13 +2,15 @@
# The CPU specific programming for PiSmmCpuDxeSmm module.
#
# Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+# IMPLIED.
#
##
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 05:17:14 +0000