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| author | Laszlo Ersek <lersek@redhat.com> | 2019-09-20 10:56:47 +0200 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-02-05 12:59:32 +0000 |
| commit | d74d56fcfa31446a220f1a1145d61d3f36445580 (patch) | |
| tree | f9704188b2128c1c791ac255bbb67afa406a09da /OvmfPkg/OvmfPkg.dec | |
| parent | 422da35375c6d95dae9d5c56530d255b672b1f59 (diff) | |
| download | edk2-d74d56fcfa31446a220f1a1145d61d3f36445580.tar.gz edk2-d74d56fcfa31446a220f1a1145d61d3f36445580.tar.bz2 edk2-d74d56fcfa31446a220f1a1145d61d3f36445580.zip | |
OvmfPkg: introduce PcdQ35SmramAtDefaultSmbase
For supporting VCPU hotplug with SMM enabled/required, QEMU offers the
(dynamically detectable) feature called "SMRAM at default SMBASE". When
the feature is enabled, the firmware can lock down the 128 KB range
starting at the default SMBASE; that is, the [0x3_0000, 0x4_FFFF]
interval. The goal is to shield the very first SMI handler of the
hotplugged VCPU from OS influence.
Multiple modules in OVMF will have to inter-operate for locking down this
range. Introduce a dynamic PCD that will reflect the feature (to be
negotiated by PlatformPei), for coordination between drivers.
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1512
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Message-Id: <20200129214412.2361-2-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Diffstat (limited to 'OvmfPkg/OvmfPkg.dec')
| -rw-r--r-- | OvmfPkg/OvmfPkg.dec | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index d5fee805ef..57034c784f 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -257,6 +257,12 @@ # This PCD is only accessed if PcdSmmSmramRequire is TRUE (see below).
gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT16|0x20
+ ## Set to TRUE by PlatformPei if the Q35 board supports the "SMRAM at default
+ # SMBASE" feature.
+ #
+ # This PCD is only accessed if PcdSmmSmramRequire is TRUE (see below).
+ gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase|FALSE|BOOLEAN|0x34
+
[PcdsFeatureFlag]
gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0x1c
gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN|0x1d
|