OvmfPkg: PlatformPei: lower the 32-bit PCI MMIO base to 2GB on Q35

Gerd has advised us that long term support Q35 machine types have no low
RAM above 2GB, hence we should utilize the [2GB, 3GB) gap -- that we
currently leave unused -- for MMIO. (Plus, later in this series, for the
PCIEXBAR too.)

Cc: Gabriel Somlo <somlo@cmu.edu>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Marcel Apfelbaum <marcel@redhat.com>
Cc: Michał Zegan <webczat_200@poczta.onet.pl>
Ref: https://github.com/tianocore/edk2/issues/32
Ref: http://thread.gmane.org/gmane.comp.bios.edk2.devel/8707/focus=8817
Suggested-by: Gerd Hoffmann <kraxel@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Gabriel Somlo <somlo@cmu.edu>
Tested-by: Michał Zegan <webczat_200@poczta.onet.pl>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

1 files changed, 3 insertions, 4 deletions

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 7d0941209f..8e4da41001 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -218,11 +218,10 @@ MemMapInitialization (
     TopOfLowRam = GetSystemMemorySizeBelow4gb ();

     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {

       //

-      // A 3GB base will always fall into Q35's 32-bit PCI host aperture,

-      // regardless of the Q35 MMCONFIG BAR. Correspondingly, QEMU never lets

-      // the RAM below 4 GB exceed it.

+      // On Q35 machine types that QEMU intends to support in the long term,

+      // QEMU never lets the RAM below 4 GB exceed 2 GB.

       //

-      PciBase = BASE_2GB + BASE_1GB;

+      PciBase = BASE_2GB;

       ASSERT (TopOfLowRam <= PciBase);

     } else {

       PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;