Revert "OvmfPkg/PlatformPei: fix MTRR for low-RAM sizes that have many bits clear"

This reverts commit 39b9a5ffe6618b7870be2a54fe7725000249c33a.

The original fix for <https://bugzilla.tianocore.org/show_bug.cgi?id=1814>
triggered a bug / incorrect assumption in QEMU.

QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above
it. When the firmware doesn't satisfy this assumption, QEMU generates an
\_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the
firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign
32-bit MMIO BARs.

Working around the problem in the firmware looks less problematic than
fixing QEMU. Revert the original changes first, before implementing an
alternative fix.

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>

3 files changed, 7 insertions, 24 deletions

diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index ae73c63d27..e890e36408 100644
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -42,8 +42,6 @@ STATIC UINT32 mS3AcpiReservedMemorySize;
 

 STATIC UINT16 mQ35TsegMbytes;

 

-UINT32 mQemuUc32Base;

-

 VOID

 Q35TsegMbytesInitialization (

   VOID

@@ -665,8 +663,6 @@ QemuInitializeRam (
   // cover it exactly.

   //

   if (IsMtrrSupported ()) {

-    UINT32 Uc32Size;

-

     MtrrGetAllMtrrs (&MtrrSettings);

 

     //

@@ -693,24 +689,11 @@ QemuInitializeRam (
 

     //

     // Set memory range from the "top of lower RAM" (RAM below 4GB) to 4GB as

-    // uncacheable. Make sure one variable MTRR suffices by truncating the size

-    // to a whole power of two. This will round the base *up*, and a gap (not

-    // used for either RAM or MMIO) may stay in the middle, marked as

-    // cacheable-by-default.

-    //

-    Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize));

-    mQemuUc32Base = (UINT32)(SIZE_4GB - Uc32Size);

-    if (mQemuUc32Base != LowerMemorySize) {

-      DEBUG ((DEBUG_VERBOSE, "%a: rounded UC32 base from 0x%x up to 0x%x, for "

-        "an UC32 size of 0x%x\n", __FUNCTION__, (UINT32)LowerMemorySize,

-        mQemuUc32Base, Uc32Size));

-    }

-

-    Status = MtrrSetMemoryAttribute (mQemuUc32Base, Uc32Size,

-               CacheUncacheable);

+    // uncacheable

+    //

+    Status = MtrrSetMemoryAttribute (LowerMemorySize,

+               SIZE_4GB - LowerMemorySize, CacheUncacheable);

     ASSERT_EFI_ERROR (Status);

-  } else {

-    mQemuUc32Base = (UINT32)LowerMemorySize;

   }

 }

 

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index c064b4ed9b..fd8eccaf3e 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -174,12 +174,14 @@ MemMapInitialization (
   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);

 

   if (!mXen) {

+    UINT32  TopOfLowRam;

     UINT64  PciExBarBase;

     UINT32  PciBase;

     UINT32  PciSize;

 

+    TopOfLowRam = GetSystemMemorySizeBelow4gb ();

     PciExBarBase = 0;

-    PciBase = (mQemuUc32Base < BASE_2GB) ? BASE_2GB : mQemuUc32Base;

+    PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;

     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {

       //

       // The 32-bit PCI host aperture is expected to fall between the top of

diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h
index 4476ddd871..81af8b7148 100644
--- a/OvmfPkg/PlatformPei/Platform.h
+++ b/OvmfPkg/PlatformPei/Platform.h
@@ -114,6 +114,4 @@ extern UINT32 mMaxCpuCount;
 

 extern UINT16 mHostBridgeDevId;

 

-extern UINT32 mQemuUc32Base;

-

 #endif // _PLATFORM_PEI_H_INCLUDED_