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| author | Laszlo Ersek <lersek@redhat.com> | 2019-09-20 14:02:14 +0200 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-02-05 12:59:32 +0000 |
| commit | 73974f809cbfc2b4cecec539b2eb8635b0e42eff (patch) | |
| tree | d09540c6f675c5b5cb13781ca8d686ad74b64d3b /OvmfPkg/PlatformPei | |
| parent | e0ed7a9b15fa777b216ee1af01502b5dc93da1b1 (diff) | |
| download | edk2-73974f809cbfc2b4cecec539b2eb8635b0e42eff.tar.gz edk2-73974f809cbfc2b4cecec539b2eb8635b0e42eff.tar.bz2 edk2-73974f809cbfc2b4cecec539b2eb8635b0e42eff.zip | |
OvmfPkg/PlatformPei: detect SMRAM at default SMBASE (skeleton)
Introduce the Q35SmramAtDefaultSmbaseInitialization() function for
detecting the "SMRAM at default SMBASE" feature.
For now, the function is only a skeleton, so that we can gradually build
upon the result while the result is hard-coded as FALSE. The actual
detection will occur in a later patch.
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1512
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Message-Id: <20200129214412.2361-6-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Diffstat (limited to 'OvmfPkg/PlatformPei')
| -rw-r--r-- | OvmfPkg/PlatformPei/MemDetect.c | 18 | ||||
| -rw-r--r-- | OvmfPkg/PlatformPei/Platform.c | 1 | ||||
| -rw-r--r-- | OvmfPkg/PlatformPei/Platform.h | 7 | ||||
| -rw-r--r-- | OvmfPkg/PlatformPei/PlatformPei.inf | 1 |
4 files changed, 27 insertions, 0 deletions
diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c index 58b171fba1..2bc1c46dff 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -43,6 +43,8 @@ STATIC UINT32 mS3AcpiReservedMemorySize; STATIC UINT16 mQ35TsegMbytes;
+BOOLEAN mQ35SmramAtDefaultSmbase;
+
UINT32 mQemuUc32Base;
VOID
@@ -91,6 +93,22 @@ Q35TsegMbytesInitialization ( VOID
+Q35SmramAtDefaultSmbaseInitialization (
+ VOID
+ )
+{
+ RETURN_STATUS PcdStatus;
+
+ ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);
+
+ mQ35SmramAtDefaultSmbase = FALSE;
+ PcdStatus = PcdSetBoolS (PcdQ35SmramAtDefaultSmbase,
+ mQ35SmramAtDefaultSmbase);
+ ASSERT_RETURN_ERROR (PcdStatus);
+}
+
+
+VOID
QemuUc32BaseInitialization (
VOID
)
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 510d6d7477..473af10278 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -792,6 +792,7 @@ InitializePlatform ( if (FeaturePcdGet (PcdSmmSmramRequire)) {
Q35BoardVerification ();
Q35TsegMbytesInitialization ();
+ Q35SmramAtDefaultSmbaseInitialization ();
}
PublishPeiMemory ();
diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h index 2f3cebcd3a..43f20f067f 100644 --- a/OvmfPkg/PlatformPei/Platform.h +++ b/OvmfPkg/PlatformPei/Platform.h @@ -52,6 +52,11 @@ Q35TsegMbytesInitialization ( VOID
);
+VOID
+Q35SmramAtDefaultSmbaseInitialization (
+ VOID
+ );
+
EFI_STATUS
PublishPeiMemory (
VOID
@@ -119,6 +124,8 @@ extern UINT32 mMaxCpuCount; extern UINT16 mHostBridgeDevId;
+extern BOOLEAN mQ35SmramAtDefaultSmbase;
+
extern UINT32 mQemuUc32Base;
#endif // _PLATFORM_PEI_H_INCLUDED_
diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/PlatformPei.inf index 30eaebdfae..25229618ed 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -84,6 +84,7 @@ gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd
gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes
+ gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase
gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
|