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| author | Laszlo Ersek <lersek@redhat.com> | 2016-05-09 22:54:36 +0200 |
|---|---|---|
| committer | Laszlo Ersek <lersek@redhat.com> | 2016-05-17 20:48:43 +0200 |
| commit | bba734ab4c7c9b4386d39420983bf61484f65dda (patch) | |
| tree | 6d990c52951f16e583de23d7ec9fb3a7603f6933 /OvmfPkg/PlatformPei | |
| parent | c4df7fd01ff46cce6baa0afcc0f32f60bd2b5ace (diff) | |
| download | edk2-bba734ab4c7c9b4386d39420983bf61484f65dda.tar.gz edk2-bba734ab4c7c9b4386d39420983bf61484f65dda.tar.bz2 edk2-bba734ab4c7c9b4386d39420983bf61484f65dda.zip | |
OvmfPkg/PlatformPei: provide 10 * 4KB of PCI IO Port space on Q35
This can accommodate 10 bridges (including root bridges, PCIe upstream and
downstream ports, etc -- see
<https://bugzilla.redhat.com/show_bug.cgi?id=1333238#c12> for more
details).
10 is not a whole lot, but closer to the architectural limit of 15 than
our current 4, so it can be considered a stop-gap solution until all
guests manage to migrate to virtio-1.0, and no longer need PCI IO BARs
behind PCIe downstream ports.
Cc: Gabriel Somlo <somlo@cmu.edu>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1333238
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Gabriel Somlo <somlo@cmu.edu>
Diffstat (limited to 'OvmfPkg/PlatformPei')
| -rw-r--r-- | OvmfPkg/PlatformPei/Platform.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index b03b577013..75f7480ac7 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -244,6 +244,16 @@ MemMapInitialization ( EfiReservedMemoryType);
}
AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
+
+ //
+ // On Q35, the IO Port space is available for PCI resource allocations from
+ // 0x6000 up.
+ //
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
+ PciIoBase = 0x6000;
+ PciIoSize = 0xA000;
+ ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);
+ }
}
//
|