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| author | Min Xu <min.m.xu@intel.com> | 2022-03-06 22:35:23 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-04-02 08:15:12 +0000 |
| commit | f53f449f15ddae8b2398b9419ba40186e6608ea3 (patch) | |
| tree | 76e051902d0e8c57f74921b6d7d0274d8eb96b04 /OvmfPkg/PlatformPei | |
| parent | cec82a64cfd40ca0858cdc7bfd57c4115716b639 (diff) | |
| download | edk2-f53f449f15ddae8b2398b9419ba40186e6608ea3.tar.gz edk2-f53f449f15ddae8b2398b9419ba40186e6608ea3.tar.bz2 edk2-f53f449f15ddae8b2398b9419ba40186e6608ea3.zip | |
OvmfPkg/PlatformPei: Refactor MiscInitialization
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863
MiscInitialization is split into 2 functions:
- PlatformMiscInitialization is for PlatformInitLib.
- MiscInitialization calls PlatformMiscInitialization and then sets
PCD. It is for PlatformPei.
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Sebastien Boeuf <sebastien.boeuf@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
Diffstat (limited to 'OvmfPkg/PlatformPei')
| -rw-r--r-- | OvmfPkg/PlatformPei/Platform.c | 43 |
1 files changed, 26 insertions, 17 deletions
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index e91acca9f7..02697c473d 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -57,12 +57,12 @@ PlatformMemMapInitialization ( IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
)
{
- UINT64 PciIoBase;
- UINT64 PciIoSize;
- UINT32 TopOfLowRam;
- UINT64 PciExBarBase;
- UINT32 PciBase;
- UINT32 PciSize;
+ UINT64 PciIoBase;
+ UINT64 PciIoSize;
+ UINT32 TopOfLowRam;
+ UINT64 PciExBarBase;
+ UINT32 PciBase;
+ UINT32 PciSize;
PciIoBase = 0xC000;
PciIoSize = 0x4000;
@@ -360,17 +360,16 @@ MiscInitializationForMicrovm ( }
VOID
-MiscInitialization (
+PlatformMiscInitialization (
IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
)
{
- UINTN PmCmd;
- UINTN Pmba;
- UINT32 PmbaAndVal;
- UINT32 PmbaOrVal;
- UINTN AcpiCtlReg;
- UINT8 AcpiEnBit;
- RETURN_STATUS PcdStatus;
+ UINTN PmCmd;
+ UINTN Pmba;
+ UINT32 PmbaAndVal;
+ UINT32 PmbaOrVal;
+ UINTN AcpiCtlReg;
+ UINT8 AcpiEnBit;
//
// Disable A20 Mask
@@ -417,9 +416,6 @@ MiscInitialization ( return;
}
- PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, PlatformInfoHob->HostBridgeDevId);
- ASSERT_RETURN_ERROR (PcdStatus);
-
if (PlatformInfoHob->HostBridgeDevId == CLOUDHV_DEVICE_ID) {
DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor is done.\n", __FUNCTION__));
return;
@@ -465,6 +461,19 @@ MiscInitialization ( }
VOID
+MiscInitialization (
+ IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
+ )
+{
+ RETURN_STATUS PcdStatus;
+
+ PlatformMiscInitialization (PlatformInfoHob);
+
+ PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, PlatformInfoHob->HostBridgeDevId);
+ ASSERT_RETURN_ERROR (PcdStatus);
+}
+
+VOID
BootModeInitialization (
IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
)
|