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| author | Tom Lendacky <thomas.lendacky@amd.com> | 2021-01-07 12:48:15 -0600 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-01-07 19:34:39 +0000 |
| commit | 3b32be7e7192654812eb35bd89255f2916b1f02a (patch) | |
| tree | 5fc27b068c798733e93f15d043c9cb7b91d31c54 /OvmfPkg/ResetVector/Ia32 | |
| parent | bd0c1c8e225b1274fc7e3f154811af40619e3f04 (diff) | |
| download | edk2-3b32be7e7192654812eb35bd89255f2916b1f02a.tar.gz edk2-3b32be7e7192654812eb35bd89255f2916b1f02a.tar.bz2 edk2-3b32be7e7192654812eb35bd89255f2916b1f02a.zip | |
OvmfPkg/ResetVector: Save the encryption mask at boot time
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3108
The early assembler code performs validation for some of the SEV-related
information, specifically the encryption bit position. To avoid having to
re-validate the encryption bit position as the system proceeds through its
boot phases, save the validated encryption bit position in the SEV-ES work
area for use by later phases.
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <2609724859cf21f0c6d45bc323e94465dca4e621.1610045305.git.thomas.lendacky@amd.com>
Diffstat (limited to 'OvmfPkg/ResetVector/Ia32')
| -rw-r--r-- | OvmfPkg/ResetVector/Ia32/PageTables64.asm | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/OvmfPkg/ResetVector/Ia32/PageTables64.asm b/OvmfPkg/ResetVector/Ia32/PageTables64.asm index a1771dfdec..5fae8986d9 100644 --- a/OvmfPkg/ResetVector/Ia32/PageTables64.asm +++ b/OvmfPkg/ResetVector/Ia32/PageTables64.asm @@ -145,7 +145,7 @@ GetSevEncBit: ; The encryption bit position is always above 31
sub ebx, 32
- jns SevExit
+ jns SevSaveMask
; Encryption bit was reported as 31 or below, enter a HLT loop
SevEncBitLowHlt:
@@ -153,6 +153,14 @@ SevEncBitLowHlt: hlt
jmp SevEncBitLowHlt
+SevSaveMask:
+ xor edx, edx
+ bts edx, ebx
+
+ mov dword[SEV_ES_WORK_AREA_ENC_MASK], 0
+ mov dword[SEV_ES_WORK_AREA_ENC_MASK + 4], edx
+ jmp SevExit
+
NoSev:
;
; Perform an SEV-ES sanity check by seeing if a #VC exception occurred.
|