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| author | Sunil V L <sunilvl@ventanamicro.com> | 2023-04-18 10:53:39 +0530 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-06-23 04:49:11 +0000 |
| commit | 37423fa344ee3381e019055502f9b6363d8bbd40 (patch) | |
| tree | 2b7f49fb9885e1e11813b53cfa54a0fe533c1ae7 /OvmfPkg/RiscVVirt | |
| parent | 420cd549930a9e62df8529aee28226cbe189f71f (diff) | |
| download | edk2-37423fa344ee3381e019055502f9b6363d8bbd40.tar.gz edk2-37423fa344ee3381e019055502f9b6363d8bbd40.tar.bz2 edk2-37423fa344ee3381e019055502f9b6363d8bbd40.zip | |
OvmfPkg/RiscVVirt: Add support for separate code and variable store
Currently, RiscVVirtQemu supports unified code and variable store
mainly because only one pflash devices was available in qemu for
EDK2. However, this doesn't allow to map the code part as read-only.
With recent qemu enhancements, it is now possible for EDK2 to make
use of both pflash devices in RISC-V virt machine. So, add support
to create code and vars images separately. This also allows easy
firmware code updates without losing the variable store.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Cc: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Diffstat (limited to 'OvmfPkg/RiscVVirt')
| -rw-r--r-- | OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc | 14 | ||||
| -rw-r--r-- | OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 2 | ||||
| -rw-r--r-- | OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 16 |
3 files changed, 19 insertions, 13 deletions
diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc b/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc index b0a1c3293f..eba612372f 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc +++ b/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc @@ -10,16 +10,14 @@ [Defines]
DEFINE BLOCK_SIZE = 0x1000
+DEFINE PFLASH0_BASE = 0x20000000
DEFINE PFLASH1_BASE = 0x22000000
-DEFINE FW_BASE_ADDRESS = $(PFLASH1_BASE)
-DEFINE FW_SIZE = 0x00800000
-DEFINE FW_BLOCKS = 0x800
-
-DEFINE CODE_BASE_ADDRESS = $(FW_BASE_ADDRESS)
-DEFINE CODE_SIZE = 0x00740000
-DEFINE CODE_BLOCKS = 0x740
+DEFINE CODE_BASE_ADDRESS = $(PFLASH0_BASE)
+DEFINE CODE_SIZE = 0x00800000
+DEFINE CODE_BLOCKS = 0x800
+DEFINE VARS_BASE_ADDRESS = $(PFLASH1_BASE)
DEFINE VARS_SIZE = 0x000C0000
DEFINE VARS_BLOCK_SIZE = 0x40000
DEFINE VARS_BLOCKS = 0x3
@@ -29,7 +27,7 @@ DEFINE VARS_BLOCKS = 0x3 # The total size of EFI Variable FD must include
# all of sub regions of EFI Variable
#
-DEFINE VARS_OFFSET = $(CODE_SIZE)
+DEFINE VARS_OFFSET = 0x00000000
DEFINE VARS_LIVE_SIZE = 0x00040000
DEFINE VARS_FTW_WORKING_OFFSET = $(VARS_OFFSET) + $(VARS_LIVE_SIZE)
DEFINE VARS_FTW_WORKING_SIZE = 0x00040000
diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc index 414d186179..04573bc0f3 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc @@ -85,7 +85,7 @@ QemuLoadImageLib|OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLib.inf
TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
- VirtNorFlashPlatformLib|OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.inf
+ VirtNorFlashPlatformLib|OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTreeLib.inf
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf index 354c9271d1..21e4ba6737 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf @@ -12,17 +12,25 @@ !include RiscVVirt.fdf.inc
################################################################################
-[FD.RISCV_VIRT]
-BaseAddress = $(FW_BASE_ADDRESS)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress
-Size = $(FW_SIZE)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize
+[FD.RISCV_VIRT_CODE]
+BaseAddress = $(CODE_BASE_ADDRESS)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress
+Size = $(CODE_SIZE)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize
ErasePolarity = 1
BlockSize = $(BLOCK_SIZE)
-NumBlocks = $(FW_BLOCKS)
+NumBlocks = $(CODE_BLOCKS)
0x00000000|$(CODE_SIZE)
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize
FV = FVMAIN_COMPACT
+################################################################################
+[FD.RISCV_VIRT_VARS]
+BaseAddress = $(VARS_BASE_ADDRESS)
+Size = $(VARS_SIZE)
+ErasePolarity = 1
+BlockSize = $(VARS_BLOCK_SIZE)
+NumBlocks = $(VARS_BLOCKS)
+
!include VarStore.fdf.inc
################################################################################
|