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| author | Heinrich Schuchardt <heinrich.schuchardt@canonical.com> | 2024-09-16 23:12:18 +0200 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2024-10-04 04:53:21 +0000 |
| commit | f8c738577f813bbe6cb017cfbb29b70582ab32b4 (patch) | |
| tree | 912940249114ed2b0d925ad527a577cbd3cf172e /OvmfPkg/RiscVVirt | |
| parent | 28dd588ca80c61c4bea9294785d5d884ad3f2c41 (diff) | |
| download | edk2-f8c738577f813bbe6cb017cfbb29b70582ab32b4.tar.gz edk2-f8c738577f813bbe6cb017cfbb29b70582ab32b4.tar.bz2 edk2-f8c738577f813bbe6cb017cfbb29b70582ab32b4.zip | |
UefiCpuPkg: RiscV64: initialize FPU
The OpenSSL library uses floating point registers.
The is no guarantee that a prior firmware stage has enabled the FPU.
Provide a library BaseRiscVFpuLib to
* Enable the FPU and set it to state 'dirty'.
* Clear the fcsr CSR.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Diffstat (limited to 'OvmfPkg/RiscVVirt')
0 files changed, 0 insertions, 0 deletions