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author | Anthony PERARD <anthony.perard@citrix.com> | 2019-08-13 12:30:50 +0100 |
---|---|---|
committer | Laszlo Ersek <lersek@redhat.com> | 2019-08-21 18:03:49 +0200 |
commit | a8c791c15be599f5a48f8a70b040fbe0cd3232c0 (patch) | |
tree | 2a7ca2c3f9fc6134bca9ed3ab9b6583a5610ba90 /OvmfPkg/XenResetVector/Ia32 | |
parent | 1e9d6b0f98b53498f8ae4104502da087493eba2c (diff) | |
download | edk2-a8c791c15be599f5a48f8a70b040fbe0cd3232c0.tar.gz edk2-a8c791c15be599f5a48f8a70b040fbe0cd3232c0.tar.bz2 edk2-a8c791c15be599f5a48f8a70b040fbe0cd3232c0.zip |
OvmfPkg/XenResetVector: Add new entry point for Xen PVH
Add a new entry point for Xen PVH that enter directly in 32bits.
Information on the expected state of the machine when this entry point
is used can be found at:
https://xenbits.xenproject.org/docs/unstable/misc/pvh.html
Also, compare to the original file [1], the two `nop' of the "resetVector"
entry point are removed. There were introduced by 8332983e2e33
("UefiCpuPkg: Replace the un-necessary WBINVD instruction at the reset
vector with two NOPs in VTF0.", 2011-08-04), but don't seems to be
useful. This is the entry point used by HVM guest (hvmloader).
[1] UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1689
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20190813113119.14804-7-anthony.perard@citrix.com>
Diffstat (limited to 'OvmfPkg/XenResetVector/Ia32')
-rw-r--r-- | OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm b/OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm new file mode 100644 index 0000000000..2a17fed52f --- /dev/null +++ b/OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm @@ -0,0 +1,49 @@ +;------------------------------------------------------------------------------
+; @file
+; An entry point use by Xen when a guest is started in PVH mode.
+;
+; Copyright (c) 2019, Citrix Systems, Inc.
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+BITS 32
+
+xenPVHMain:
+ ;
+ ; 'BP' to indicate boot-strap processor
+ ;
+ mov di, 'BP'
+
+ ;
+ ; ESP will be used as initial value of the EAX register
+ ; in Main.asm
+ ;
+ xor esp, esp
+
+ mov ebx, ADDR_OF(gdtr)
+ lgdt [ebx]
+
+ mov eax, SEC_DEFAULT_CR0
+ mov cr0, eax
+
+ jmp LINEAR_CODE_SEL:ADDR_OF(.jmpToNewCodeSeg)
+.jmpToNewCodeSeg:
+
+ mov eax, SEC_DEFAULT_CR4
+ mov cr4, eax
+
+ mov ax, LINEAR_SEL
+ mov ds, ax
+ mov es, ax
+ mov fs, ax
+ mov gs, ax
+ mov ss, ax
+
+ ;
+ ; Jump to the main routine of the pre-SEC code
+ ; skiping the 16-bit part of the routine and
+ ; into the 32-bit flat mode part
+ ;
+ OneTimeCallRet TransitionFromReal16To32BitFlat
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