OvmfPkg/PlatformPei: rebase and resize the permanent PEI memory for S3

Move the permanent PEI memory for the S3 resume boot path to the top of
the low RAM (just below TSEG if the SMM driver stack is included in the
build). The new size is derived from CpuMpPei's approximate memory demand.

Save the base address and the size in new global variables, regardless of
the boot path. On the normal boot path, use these variables for covering
the area with EfiACPIMemoryNVS type memory.

PcdS3AcpiReservedMemoryBase and PcdS3AcpiReservedMemorySize become unused
in PlatformPei; remove them.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

2 files changed, 30 insertions, 14 deletions

diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index d59b461547..9ee4b59623 100644
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -39,6 +39,9 @@ Module Name:
 

 UINT8 mPhysMemAddressWidth;

 

+STATIC UINT32 mS3AcpiReservedMemoryBase;

+STATIC UINT32 mS3AcpiReservedMemorySize;

+

 UINT32

 GetSystemMemorySizeBelow4gb (

   VOID

@@ -335,18 +338,31 @@ PublishPeiMemory (
   UINT64                      LowerMemorySize;

   UINT32                      PeiMemoryCap;

 

+  LowerMemorySize = GetSystemMemorySizeBelow4gb ();

+  if (FeaturePcdGet (PcdSmmSmramRequire)) {

+    //

+    // TSEG is chipped from the end of low RAM

+    //

+    LowerMemorySize -= FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB;

+  }

+

+  //

+  // If S3 is supported, then the S3 permanent PEI memory is placed next,

+  // downwards. Its size is primarily dictated by CpuMpPei. The formula below

+  // is an approximation.

+  //

+  if (mS3Supported) {

+    mS3AcpiReservedMemorySize = SIZE_512KB +

+      PcdGet32 (PcdCpuMaxLogicalProcessorNumber) *

+      PcdGet32 (PcdCpuApStackSize);

+    mS3AcpiReservedMemoryBase = LowerMemorySize - mS3AcpiReservedMemorySize;

+    LowerMemorySize = mS3AcpiReservedMemoryBase;

+  }

+

   if (mBootMode == BOOT_ON_S3_RESUME) {

-    MemoryBase = PcdGet32 (PcdS3AcpiReservedMemoryBase);

-    MemorySize = PcdGet32 (PcdS3AcpiReservedMemorySize);

+    MemoryBase = mS3AcpiReservedMemoryBase;

+    MemorySize = mS3AcpiReservedMemorySize;

   } else {

-    LowerMemorySize = GetSystemMemorySizeBelow4gb ();

-    if (FeaturePcdGet (PcdSmmSmramRequire)) {

-      //

-      // TSEG is chipped from the end of low RAM

-      //

-      LowerMemorySize -= FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB;

-    }

-

     PeiMemoryCap = GetPeiMemoryCap ();

     DEBUG ((EFI_D_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",

       __FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));

@@ -514,8 +530,8 @@ InitializeRamRegions (
     // This is the memory range that will be used for PEI on S3 resume

     //

     BuildMemoryAllocationHob (

-      (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdS3AcpiReservedMemoryBase),

-      (UINT64)(UINTN) PcdGet32 (PcdS3AcpiReservedMemorySize),

+      mS3AcpiReservedMemoryBase,

+      mS3AcpiReservedMemorySize,

       EfiACPIMemoryNVS

       );

 

diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/PlatformPei.inf
index 3556404017..5d765baaeb 100644
--- a/OvmfPkg/PlatformPei/PlatformPei.inf
+++ b/OvmfPkg/PlatformPei/PlatformPei.inf
@@ -65,7 +65,6 @@
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize

   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase

   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize

-  gUefiOvmfPkgTokenSpaceGuid.PcdS3AcpiReservedMemoryBase

   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase

   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize

   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase

@@ -82,7 +81,6 @@
   gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size

   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd

   gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes

-  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize

   gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress

   gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize

   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize

@@ -95,6 +93,8 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdPropertiesTableEnable

   gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable

   gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress

+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber

+  gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize

 

 [FixedPcd]

   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress