diff options
| author | Michael Kinney <michael.d.kinney@intel.com> | 2015-12-15 19:23:57 +0000 |
|---|---|---|
| committer | mdkinney <mdkinney@Edk2> | 2015-12-15 19:23:57 +0000 |
| commit | b303605e1b7e113b4311daf161c6c3289350447b (patch) | |
| tree | 67bf068eb99ea84822f234b7194ee1084ee5455a /QuarkPlatformPkg/Platform/Pei/PlatformInit | |
| parent | 9b6bbcdbfdf5e54c6d1ed538ea8076d0858fb164 (diff) | |
| download | edk2-b303605e1b7e113b4311daf161c6c3289350447b.tar.gz edk2-b303605e1b7e113b4311daf161c6c3289350447b.tar.bz2 edk2-b303605e1b7e113b4311daf161c6c3289350447b.zip | |
QuarkPlatformPkg: Add new package for Galileo boards
Changes for V4
==============
1) Move delete of QuarkSocPkg\QuarkNorthCluster\Binary\QuarkMicrocode
from QuarkPlatformPkg commit to QuarkSocPkg commit
2) Fix incorrect license header in PlatformSecLibModStrs.uni
Changes for V3
==============
1) Set PcdResetOnMemoryTypeInformationChange FALSE in QuarkMin.dsc
This is required because QuarkMin.dsc uses the emulated variable
driver that does not preserve any non-volatile UEFI variables
across reset. If the condition is met where the memory type
information variable needs to be updated, then the system will reset
every time the UEFI Shell is run. By setting this PCD to FALSE,
then reset action is disabled.
2) Move one binary file to QuarkSocBinPkg
3) Change RMU.bin FILE statements to INF statement in DSC FD region
to be compatible with PACKAGES_PATH search for QuarkSocBinPkg
Changes for V2
==============
1) Use new generic PCI serial driver PciSioSerialDxe in MdeModulePkg
2) Configure PcdPciSerialParameters for PCI serial driver for Quark
3) Use new MtrrLib API to reduce time to set MTRRs for all DRAM
4) Convert all UNI files to utf-8
5) Replace tabs with spaces and remove trailing spaces
6) Add License.txt
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19287 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'QuarkPlatformPkg/Platform/Pei/PlatformInit')
12 files changed, 4803 insertions, 0 deletions
diff --git a/QuarkPlatformPkg/Platform/Pei/PlatformInit/BootMode.c b/QuarkPlatformPkg/Platform/Pei/PlatformInit/BootMode.c new file mode 100644 index 0000000000..0dd3d24cf3 --- /dev/null +++ b/QuarkPlatformPkg/Platform/Pei/PlatformInit/BootMode.c @@ -0,0 +1,257 @@ +/** @file
+This file provide the function to detect boot mode
+
+Copyright (c) 2013 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#include "CommonHeader.h"
+#include <Pi/PiFirmwareVolume.h>
+
+EFI_PEI_PPI_DESCRIPTOR mPpiListRecoveryBootMode = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiBootInRecoveryModePpiGuid,
+ NULL
+};
+
+/**
+ If the box was opened, it's boot with full config.
+ If the box is closed, then
+ 1. If it's first time to boot, it's boot with full config .
+ 2. If the ChassisIntrution is selected, force to be a boot with full config
+ 3. Otherwise it's boot with no change.
+
+ @param PeiServices General purpose services available to every PEIM.
+
+ @retval TRUE If it's boot with no change.
+
+ @retval FALSE If boot with no change.
+**/
+BOOLEAN
+IsBootWithNoChange (
+ IN EFI_PEI_SERVICES **PeiServices
+ )
+{
+ BOOLEAN IsFirstBoot = FALSE;
+
+ BOOLEAN EnableFastBoot = FALSE;
+ IsFirstBoot = PcdGetBool(PcdBootState);
+ EnableFastBoot = PcdGetBool (PcdEnableFastBoot);
+
+ DEBUG ((EFI_D_INFO, "IsFirstBoot = %x , EnableFastBoot= %x. \n", IsFirstBoot, EnableFastBoot));
+
+ if ((!IsFirstBoot) && EnableFastBoot) {
+ return TRUE;
+ } else {
+ return FALSE;
+ }
+}
+
+
+/**
+
+Routine Description:
+
+ This function is used to verify if the FV header is validate.
+
+ @param FwVolHeader - The FV header that to be verified.
+
+ @retval EFI_SUCCESS - The Fv header is valid.
+ @retval EFI_NOT_FOUND - The Fv header is invalid.
+
+**/
+EFI_STATUS
+ValidateFvHeader (
+ EFI_BOOT_MODE *BootMode
+ )
+{
+ UINT16 *Ptr;
+ UINT16 HeaderLength;
+ UINT16 Checksum;
+
+ EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;
+
+ if (BOOT_IN_RECOVERY_MODE == *BootMode) {
+ DEBUG ((EFI_D_INFO, "Boot mode recovery\n"));
+ return EFI_SUCCESS;
+ }
+ //
+ // Let's check whether FvMain header is valid, if not enter into recovery mode
+ //
+ //
+ // Verify the header revision, header signature, length
+ // Length of FvBlock cannot be 2**64-1
+ // HeaderLength cannot be an odd number
+ //
+ FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32(PcdFlashFvMainBase);
+ if ((FwVolHeader->Revision != EFI_FVH_REVISION)||
+ (FwVolHeader->Signature != EFI_FVH_SIGNATURE) ||
+ (FwVolHeader->FvLength == ((UINT64) -1)) ||
+ ((FwVolHeader->HeaderLength & 0x01) != 0)
+ ) {
+ return EFI_NOT_FOUND;
+ }
+ //
+ // Verify the header checksum
+ //
+ HeaderLength = (UINT16) (FwVolHeader->HeaderLength / 2);
+ Ptr = (UINT16 *) FwVolHeader;
+ Checksum = 0;
+ while (HeaderLength > 0) {
+ Checksum = Checksum +*Ptr;
+ Ptr++;
+ HeaderLength--;
+ }
+
+ if (Checksum != 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+
+ Check whether go to recovery path
+ @retval TRUE Go to recovery path
+ @retval FALSE Go to normal path
+
+**/
+BOOLEAN
+OemRecoveryBootMode ()
+{
+ return PlatformIsBootWithRecoveryStage1 ();
+}
+
+/**
+ Peform the boot mode determination logic
+ If the box is closed, then
+ 1. If it's first time to boot, it's boot with full config .
+ 2. If the ChassisIntrution is selected, force to be a boot with full config
+ 3. Otherwise it's boot with no change.
+
+ @param PeiServices General purpose services available to every PEIM.
+
+ @param BootMode The detected boot mode.
+
+ @retval EFI_SUCCESS if the boot mode could be set
+**/
+EFI_STATUS
+UpdateBootMode (
+ IN EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_BOOT_MODE *BootMode
+ )
+{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE NewBootMode;
+ PEI_CAPSULE_PPI *Capsule;
+ CHAR8 UserSelection;
+ UINT32 Straps32;
+
+ //
+ // Read Straps. Used later if recovery boot.
+ //
+ Straps32 = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_STPDDRCFG);
+
+ //
+ // Check if we need to boot in recovery mode
+ //
+ if ((ValidateFvHeader (BootMode) != EFI_SUCCESS)) {
+ DEBUG ((EFI_D_INFO, "Force Boot mode recovery\n"));
+ NewBootMode = BOOT_IN_RECOVERY_MODE;
+ Status = PeiServicesInstallPpi (&mPpiListRecoveryBootMode);
+ ASSERT_EFI_ERROR (Status);
+ if (OemRecoveryBootMode () == FALSE) {
+ DEBUG ((EFI_D_INFO, "Recovery stage1 not Active, reboot to activate recovery stage1 image\n"));
+ OemInitiateRecoveryAndWait ();
+ }
+ } else if (OemRecoveryBootMode ()) {
+ DEBUG ((EFI_D_INFO, "Boot mode recovery\n"));
+ NewBootMode = BOOT_IN_RECOVERY_MODE;
+ Status = PeiServicesInstallPpi (&mPpiListRecoveryBootMode);
+ ASSERT_EFI_ERROR (Status);
+ } else if (QNCCheckS3AndClearState ()) {
+ //
+ // Determine if we're in capsule update mode
+ //
+ Status = PeiServicesLocatePpi (
+ &gPeiCapsulePpiGuid,
+ 0,
+ NULL,
+ (VOID **)&Capsule
+ );
+ if (Status == EFI_SUCCESS) {
+ Status = Capsule->CheckCapsuleUpdate (PeiServices);
+ if (Status == EFI_SUCCESS) {
+ DEBUG ((EFI_D_INFO, "Boot mode Flash Update\n"));
+ NewBootMode = BOOT_ON_FLASH_UPDATE;
+ } else {
+ DEBUG ((EFI_D_INFO, "Boot mode S3 resume\n"));
+ NewBootMode = BOOT_ON_S3_RESUME;
+ }
+ } else {
+ DEBUG ((EFI_D_INFO, "Boot mode S3 resume\n"));
+ NewBootMode = BOOT_ON_S3_RESUME;
+ }
+ } else {
+ //
+ // Check if this is a power on reset
+ //
+ if (QNCCheckPowerOnResetAndClearState ()) {
+ DEBUG ((EFI_D_INFO, "Power On Reset\n"));
+ }
+ if (IsBootWithNoChange (PeiServices)) {
+ DEBUG ((EFI_D_INFO, "Boot with Minimum cfg\n"));
+ NewBootMode = BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
+ } else {
+ DEBUG ((EFI_D_INFO, "Boot with Full cfg\n"));
+ NewBootMode = BOOT_WITH_FULL_CONFIGURATION;
+ }
+ }
+ *BootMode = NewBootMode;
+ Status = PeiServicesSetBootMode (NewBootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // If Recovery Boot then prompt the user to insert a USB key with recovery nodule and
+ // continue with the recovery. Also give the user a chance to retry a normal boot.
+ //
+ if (NewBootMode == BOOT_IN_RECOVERY_MODE) {
+ if ((Straps32 & B_STPDDRCFG_FORCE_RECOVERY) == 0) {
+ DEBUG ((EFI_D_ERROR, "*****************************************************************\n"));
+ DEBUG ((EFI_D_ERROR, "***** Force Recovery Jumper Detected. *****\n"));
+ DEBUG ((EFI_D_ERROR, "***** Attempting auto recovery of system flash. *****\n"));
+ DEBUG ((EFI_D_ERROR, "***** Expecting USB key with recovery module connected. *****\n"));
+ DEBUG ((EFI_D_ERROR, "***** PLEASE REMOVE FORCE RECOVERY JUMPER. *****\n"));
+ DEBUG ((EFI_D_ERROR, "*****************************************************************\n"));
+ } else {
+ DEBUG ((EFI_D_ERROR, "*****************************************************************\n"));
+ DEBUG ((EFI_D_ERROR, "***** ERROR: System boot failure!!!!!!! *****\n"));
+ DEBUG ((EFI_D_ERROR, "***** - Press 'R' if you wish to force system recovery *****\n"));
+ DEBUG ((EFI_D_ERROR, "***** (connect USB key with recovery module first) *****\n"));
+ DEBUG ((EFI_D_ERROR, "***** - Press any other key to attempt another boot *****\n"));
+ DEBUG ((EFI_D_ERROR, "*****************************************************************\n"));
+
+ UserSelection = PlatformDebugPortGetChar8 ();
+ if ((UserSelection != 'R') && (UserSelection != 'r')) {
+ DEBUG ((EFI_D_ERROR, "New boot attempt selected........\n"));
+ //
+ // Initialte the cold reset
+ //
+ ResetCold ();
+ }
+ DEBUG ((EFI_D_ERROR, "Recovery boot selected..........\n"));
+ }
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/QuarkPlatformPkg/Platform/Pei/PlatformInit/CommonHeader.h b/QuarkPlatformPkg/Platform/Pei/PlatformInit/CommonHeader.h new file mode 100644 index 0000000000..3630f347b6 --- /dev/null +++ b/QuarkPlatformPkg/Platform/Pei/PlatformInit/CommonHeader.h @@ -0,0 +1,84 @@ +/** @file
+Common header file shared by all source files.
+
+This file includes package header files, library classes and protocol, PPI & GUID definitions.
+
+Copyright (c) 2013 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef __COMMON_HEADER_H_
+#define __COMMON_HEADER_H_
+
+
+
+#include <PiPei.h>
+#include <IntelQNCPeim.h>
+#include "Ioh.h"
+#include <Platform.h>
+#include <PlatformBoards.h>
+
+#include <IndustryStandard/SmBus.h>
+#include <IndustryStandard/Pci22.h>
+
+#include <Guid/AcpiS3Context.h>
+#include <Ppi/AtaController.h>
+#include <Guid/Capsule.h>
+#include <Ppi/MasterBootMode.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Guid/RecoveryDevice.h>
+#include <Guid/MemoryConfigData.h>
+#include <Guid/MemoryOverwriteControl.h>
+#include <Guid/CapsuleVendor.h>
+#include <Guid/QuarkCapsuleGuid.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Ppi/FvLoadFile.h>
+#include <Guid/SmramMemoryReserve.h>
+#include <Ppi/DeviceRecoveryModule.h>
+#include <Ppi/Capsule.h>
+#include <Ppi/Reset.h>
+#include <Ppi/Stall.h>
+#include <Ppi/BootInRecoveryMode.h>
+#include <Guid/FirmwareFileSystem2.h>
+#include <Ppi/MemoryDiscovered.h>
+#include <Ppi/RecoveryModule.h>
+#include <Ppi/Smbus2.h>
+#include <Ppi/FirmwareVolumeInfo.h>
+#include <Ppi/EndOfPeiPhase.h>
+
+#include <Library/DebugLib.h>
+#include <Library/PeimEntryPoint.h>
+#include <Library/BaseLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/HobLib.h>
+#include <Library/PciCf8Lib.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Library/ReportStatusCodeLib.h>
+#include <Library/IntelQNCLib.h>
+#include <Library/PcdLib.h>
+#include <Library/SmbusLib.h>
+#include <Library/RecoveryOemHookLib.h>
+#include <Library/TimerLib.h>
+#include <Library/PrintLib.h>
+#include <Library/ResetSystemLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PerformanceLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/MtrrLib.h>
+#include <Library/QNCAccessLib.h>
+#include <Library/PlatformHelperLib.h>
+#include <Library/PlatformPcieHelperLib.h>
+
+#include <Register/Cpuid.h>
+
+#endif
diff --git a/QuarkPlatformPkg/Platform/Pei/PlatformInit/Generic/Recovery.c b/QuarkPlatformPkg/Platform/Pei/PlatformInit/Generic/Recovery.c new file mode 100644 index 0000000000..ea67ba9d63 --- /dev/null +++ b/QuarkPlatformPkg/Platform/Pei/PlatformInit/Generic/Recovery.c @@ -0,0 +1,501 @@ +/** @file
+Install Platform EFI_PEI_RECOVERY_MODULE_PPI and Implementation of
+EFI_PEI_LOAD_RECOVERY_CAPSULE service.
+
+Copyright (c) 2013 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CommonHeader.h"
+#include "PlatformEarlyInit.h"
+
+#include <Ppi/BlockIo.h>
+
+//
+// Capsule Types supported in this platform module
+//
+#include <Guid/CapsuleOnFatFloppyDisk.h>
+#include <Guid/CapsuleOnFatIdeDisk.h>
+#include <Guid/CapsuleOnFatUsbDisk.h>
+#include <Guid/CapsuleOnDataCD.h>
+#include <Guid/QuarkCapsuleGuid.h>
+
+#include <Ppi/RecoveryModule.h>
+#include <Ppi/DeviceRecoveryModule.h>
+
+#include <Library/PeiServicesLib.h>
+
+//
+// Required Service
+//
+EFI_STATUS
+EFIAPI
+PlatformRecoveryModule (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_MODULE_PPI *This
+ );
+
+VOID
+AssertNoCapsulesError (
+ IN EFI_PEI_SERVICES **PeiServices
+ );
+
+VOID
+AssertMediaDeviceError (
+ IN EFI_PEI_SERVICES **PeiServices
+ );
+
+VOID
+ReportLoadCapsuleSuccess (
+ IN EFI_PEI_SERVICES **PeiServices
+ );
+
+VOID
+CheckIfMediaPresentOnBlockIoDevice (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN OUT BOOLEAN *MediaDeviceError,
+ IN OUT BOOLEAN *MediaPresent
+ );
+
+//
+// Module globals
+//
+EFI_PEI_RECOVERY_MODULE_PPI mRecoveryPpi = { PlatformRecoveryModule };
+
+EFI_PEI_PPI_DESCRIPTOR mRecoveryPpiList = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiRecoveryModulePpiGuid,
+ &mRecoveryPpi
+};
+
+EFI_STATUS
+EFIAPI
+PeimInitializeRecovery (
+ IN EFI_PEI_SERVICES **PeiServices
+ )
+/*++
+
+Routine Description:
+
+ Provide the functionality of the Recovery Module.
+
+Arguments:
+
+ PeiServices - General purpose services available to every PEIM.
+
+Returns:
+
+ EFI_SUCCESS - If the interface could be successfully
+ installed.
+
+--*/
+{
+ EFI_STATUS Status;
+
+ Status = PeiServicesInstallPpi (&mRecoveryPpiList);
+
+ return Status;
+}
+
+EFI_STATUS
+EFIAPI
+PlatformRecoveryModule (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_MODULE_PPI *This
+ )
+/*++
+
+Routine Description:
+
+ Provide the functionality of the Platform Recovery Module.
+
+Arguments:
+
+ PeiServices - General purpose services available to every PEIM.
+ This - Pointer to EFI_PEI_RECOVERY_MODULE_PPI.
+
+Returns:
+
+ EFI_SUCCESS - If the interface could be successfully
+ installed.
+ EFI_UNSUPPORTED - Not supported.
+
+--*/
+{
+ EFI_STATUS Status;
+ EFI_PEI_DEVICE_RECOVERY_MODULE_PPI *DeviceRecoveryModule;
+ UINTN NumberOfImageProviders;
+ BOOLEAN ProviderAvailable;
+ UINTN NumberRecoveryCapsules;
+ UINTN RecoveryCapsuleSize;
+ EFI_GUID DeviceId;
+ BOOLEAN ImageFound;
+ EFI_PHYSICAL_ADDRESS Address;
+ VOID *Buffer;
+ EFI_CAPSULE_HEADER *CapsuleHeader;
+ EFI_PEI_HOB_POINTERS Hob;
+ EFI_PEI_HOB_POINTERS HobOld;
+ BOOLEAN HobUpdate;
+ EFI_FIRMWARE_VOLUME_HEADER *FvHeader;
+ UINTN Index;
+ EFI_STATUS AuthStatus;
+ EFI_GUID mEfiCapsuleHeaderGuid = QUARK_CAPSULE_GUID;
+
+ Index = 0;
+
+ Status = EFI_SUCCESS;
+ AuthStatus = EFI_SUCCESS;
+ HobUpdate = FALSE;
+
+ ProviderAvailable = TRUE;
+ ImageFound = FALSE;
+ NumberOfImageProviders = 0;
+
+ DeviceRecoveryModule = NULL;
+
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Recovery Entry\n"));
+
+ //
+ // Search the platform for some recovery capsule if the DXE IPL
+ // discovered a recovery condition and has requested a load.
+ //
+ while (ProviderAvailable) {
+
+ Status = PeiServicesLocatePpi (
+ &gEfiPeiDeviceRecoveryModulePpiGuid,
+ Index,
+ NULL,
+ (VOID **)&DeviceRecoveryModule
+ );
+
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Device Recovery PPI located\n"));
+ NumberOfImageProviders++;
+
+ Status = DeviceRecoveryModule->GetNumberRecoveryCapsules (
+ PeiServices,
+ DeviceRecoveryModule,
+ &NumberRecoveryCapsules
+ );
+
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Number Of Recovery Capsules: %d\n", NumberRecoveryCapsules));
+
+ if (NumberRecoveryCapsules == 0) {
+ Index++;
+ } else {
+ break;
+ }
+ } else {
+ ProviderAvailable = FALSE;
+ }
+ }
+ //
+ // The number of recovery capsules is 0.
+ //
+ if (!ProviderAvailable) {
+ AssertNoCapsulesError (PeiServices);
+ }
+ //
+ // If there is an image provider, get the capsule ID
+ //
+ if (ProviderAvailable) {
+ RecoveryCapsuleSize = 0;
+ if (FeaturePcdGet (PcdFrameworkCompatibilitySupport)) {
+ Status = DeviceRecoveryModule->GetRecoveryCapsuleInfo (
+ PeiServices,
+ DeviceRecoveryModule,
+ 0,
+ &RecoveryCapsuleSize,
+ &DeviceId
+ );
+ } else {
+ Status = DeviceRecoveryModule->GetRecoveryCapsuleInfo (
+ PeiServices,
+ DeviceRecoveryModule,
+ 1,
+ &RecoveryCapsuleSize,
+ &DeviceId
+ );
+
+
+ }
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Recovery Capsule Size: %d\n", RecoveryCapsuleSize));
+
+ //
+ // Only support the 2 capsule types known
+ // Future enhancement is to rank-order the selection
+ //
+ if ((!CompareGuid (&DeviceId, &gPeiCapsuleOnFatIdeDiskGuid)) &&
+ (!CompareGuid (&DeviceId, &gPeiCapsuleOnDataCDGuid)) &&
+ (!CompareGuid (&DeviceId, &gPeiCapsuleOnFatUsbDiskGuid))
+ ) {
+ return EFI_UNSUPPORTED;
+ }
+
+ Buffer = NULL;
+ Address = (UINTN) AllocatePages ((RecoveryCapsuleSize - 1) / 0x1000 + 1);
+ ASSERT (Address);
+
+ Buffer = (UINT8 *) (UINTN) Address;
+ if (FeaturePcdGet (PcdFrameworkCompatibilitySupport)) {
+ Status = DeviceRecoveryModule->LoadRecoveryCapsule (
+ PeiServices,
+ DeviceRecoveryModule,
+ 0,
+ Buffer
+ );
+ } else {
+ Status = DeviceRecoveryModule->LoadRecoveryCapsule (
+ PeiServices,
+ DeviceRecoveryModule,
+ 1,
+ Buffer
+ );
+
+ }
+
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "LoadRecoveryCapsule Returns: %r\n", Status));
+
+ if (Status == EFI_DEVICE_ERROR) {
+ AssertMediaDeviceError (PeiServices);
+ }
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ } else {
+ ReportLoadCapsuleSuccess (PeiServices);
+ }
+
+ //
+ // Update FV Hob if found
+ //
+ Buffer = (VOID *)((UINT8 *) Buffer);
+ Status = PeiServicesGetHobList ((VOID **)&Hob.Raw);
+ HobOld.Raw = Hob.Raw;
+ while (!END_OF_HOB_LIST (Hob)) {
+ if (Hob.Header->HobType == EFI_HOB_TYPE_FV) {
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Hob FV Length: %x\n", Hob.FirmwareVolume->Length));
+
+ if (Hob.FirmwareVolume->BaseAddress == (UINTN) PcdGet32 (PcdFlashFvMainBase)) {
+ HobUpdate = TRUE;
+ //
+ // This looks like the Hob we are interested in
+ //
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Hob Updated\n"));
+ Hob.FirmwareVolume->BaseAddress = (UINTN) Buffer;
+ Hob.FirmwareVolume->Length = RecoveryCapsuleSize;
+ }
+ }
+
+ Hob.Raw = GET_NEXT_HOB (Hob);
+ }
+ //
+ // Check if the top of the file is a firmware volume header
+ //
+ FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *) Buffer;
+ CapsuleHeader = (EFI_CAPSULE_HEADER *) Buffer;
+ if (FvHeader->Signature == EFI_FVH_SIGNATURE) {
+ //
+ // build FV Hob if it is not built before
+ //
+ if (!HobUpdate) {
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "FV Hob is not found, Build FV Hob then..\n"));
+ BuildFvHob (
+ (UINTN) Buffer,
+ FvHeader->FvLength
+ );
+
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Install FV Info PPI..\n"));
+
+ PeiServicesInstallFvInfoPpi (
+ NULL,
+ Buffer,
+ (UINT32) FvHeader->FvLength,
+ NULL,
+ NULL
+ );
+ }
+ //
+ // Point to the location immediately after the FV.
+ //
+ CapsuleHeader = (EFI_CAPSULE_HEADER *) ((UINT8 *) Buffer + FvHeader->FvLength);
+ }
+
+ //
+ // Check if pointer is still within the buffer
+ //
+ if ((UINTN) CapsuleHeader < (UINTN) ((UINT8 *) Buffer + RecoveryCapsuleSize)) {
+
+ //
+ // Check if it is a capsule
+ //
+ if (CompareGuid ((EFI_GUID *) CapsuleHeader, &mEfiCapsuleHeaderGuid)) {
+
+ //
+ // Set bootmode to capsule update so the capsule hob gets the right bootmode in the hob header.
+ //
+ Status = PeiServicesSetBootMode (BOOT_ON_FLASH_UPDATE);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Build capsule hob
+ //
+ BuildCvHob ((EFI_PHYSICAL_ADDRESS)(UINTN)CapsuleHeader, (UINT64)CapsuleHeader->CapsuleImageSize);
+ }
+ }
+ }
+
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Recovery Module Returning: %r\n", Status));
+ return Status;
+}
+
+/*
+ AssertNoCapsulesError:
+ There were no recovery capsules found.
+ Case 1: Report the error that no recovery block io device/media is readable and assert.
+ Case 2: Report the error that there is no media present on any recovery block io device and assert.
+ Case 3: There is media present on some recovery block io device,
+ but there is no recovery capsule on it. Report the error and assert.
+*/
+VOID
+AssertNoCapsulesError (
+ IN EFI_PEI_SERVICES **PeiServices
+ )
+{
+ BOOLEAN MediaDeviceError;
+ BOOLEAN MediaPresent;
+
+ MediaDeviceError = TRUE;
+ MediaPresent = FALSE;
+
+ CheckIfMediaPresentOnBlockIoDevice (PeiServices, &MediaDeviceError, &MediaPresent);
+/* if (MediaDeviceError) {
+ ReportStatusCode (
+ (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED),
+ (EFI_PERIPHERAL_RECOVERY_MEDIA | EFI_P_EC_MEDIA_DEVICE_ERROR)
+ );
+
+ } else if (!MediaPresent) {
+ ReportStatusCode (
+ (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED),
+ (EFI_PERIPHERAL_RECOVERY_MEDIA | EFI_P_EC_MEDIA_NOT_PRESENT)
+ );
+
+ } else {
+ ReportStatusCode (
+ (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED),
+ (EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_EC_NO_RECOVERY_CAPSULE)
+ );
+ }*/
+ //
+ // Hang.
+ //
+ CpuDeadLoop();
+}
+
+#define MAX_BLOCK_IO_PPI 32
+
+/*
+ CheckIfMediaPresentOnBlockIoDevice:
+ Checks to see whether there was a media device error or to see if there is media present.
+*/
+VOID
+CheckIfMediaPresentOnBlockIoDevice (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN OUT BOOLEAN *MediaDeviceError,
+ IN OUT BOOLEAN *MediaPresent
+ )
+{
+ EFI_STATUS Status;
+ UINTN BlockIoPpiInstance;
+ EFI_PEI_RECOVERY_BLOCK_IO_PPI *BlockIoPpi;
+ UINTN NumberBlockDevices;
+ EFI_PEI_BLOCK_IO_MEDIA Media;
+
+ *MediaDeviceError = TRUE;
+ *MediaPresent = FALSE;
+
+ for (BlockIoPpiInstance = 0; BlockIoPpiInstance < MAX_BLOCK_IO_PPI; BlockIoPpiInstance++) {
+ Status = PeiServicesLocatePpi (
+ &gEfiPeiVirtualBlockIoPpiGuid,
+ BlockIoPpiInstance,
+ NULL,
+ (VOID **)&BlockIoPpi
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // Done with all Block Io Ppis
+ //
+ break;
+ }
+
+ Status = BlockIoPpi->GetNumberOfBlockDevices (
+ PeiServices,
+ BlockIoPpi,
+ &NumberBlockDevices
+ );
+ if (EFI_ERROR (Status) || (NumberBlockDevices == 0)) {
+ continue;
+ }
+ //
+ // Just retrieve the first block
+ //
+ Status = BlockIoPpi->GetBlockDeviceMediaInfo (
+ PeiServices,
+ BlockIoPpi,
+ 0,
+ &Media
+ );
+ if (!EFI_ERROR (Status)) {
+ *MediaDeviceError = FALSE;
+ if (Media.MediaPresent) {
+ *MediaPresent = TRUE;
+ break;
+ }
+ }
+ }
+}
+
+VOID
+AssertMediaDeviceError (
+ IN EFI_PEI_SERVICES **PeiServices
+ )
+{
+/* ReportStatusCode (
+ (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED),
+ (EFI_PERIPHERAL_RECOVERY_MEDIA | EFI_P_EC_MEDIA_DEVICE_ERROR)
+ );
+*/
+ CpuDeadLoop ();
+}
+
+VOID
+ReportLoadCapsuleSuccess (
+ IN EFI_PEI_SERVICES **PeiServices
+ )
+{
+ //
+ // EFI_SW_PEI_PC_CAPSULE_START: (from the status code spec):
+ // Loaded the recovery capsule. About to hand off control to the capsule.
+ //
+/* ReportStatusCode (
+ EFI_PROGRESS_CODE,
+ (EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_CAPSULE_LOAD_SUCCESS)
+ );*/
+}
+
diff --git a/QuarkPlatformPkg/Platform/Pei/PlatformInit/MemoryCallback.c b/QuarkPlatformPkg/Platform/Pei/PlatformInit/MemoryCallback.c new file mode 100644 index 0000000000..728e2b1f6b --- /dev/null +++ b/QuarkPlatformPkg/Platform/Pei/PlatformInit/MemoryCallback.c @@ -0,0 +1,237 @@ +/** @file
+This file includes a memory call back function notified when MRC is done,
+following action is performed in this file,
+ 1. ICH initialization after MRC.
+ 2. SIO initialization.
+ 3. Install ResetSystem and FinvFv PPI.
+ 4. Set MTRR for PEI
+ 5. Create FV HOB and Flash HOB
+
+Copyright (c) 2013 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#include "CommonHeader.h"
+
+#include "PlatformEarlyInit.h"
+
+extern EFI_PEI_PPI_DESCRIPTOR mPpiStall[];
+
+EFI_PEI_RESET_PPI mResetPpi = { ResetSystem };
+
+EFI_PEI_PPI_DESCRIPTOR mPpiList[1] = {
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiResetPpiGuid,
+ &mResetPpi
+ }
+};
+
+/**
+ This function reset the entire platform, including all processor and devices, and
+ reboots the system.
+
+ @param PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS if it completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+ResetSystem (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ ResetCold();
+ return EFI_SUCCESS;
+}
+
+/**
+ This function provides a blocking stall for reset at least the given number of microseconds
+ stipulated in the final argument.
+
+ @param PeiServices General purpose services available to every PEIM.
+
+ @param this Pointer to the local data for the interface.
+
+ @param Microseconds number of microseconds for which to stall.
+
+ @retval EFI_SUCCESS the function provided at least the required stall.
+**/
+EFI_STATUS
+EFIAPI
+Stall (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_STALL_PPI *This,
+ IN UINTN Microseconds
+ )
+{
+ MicroSecondDelay (Microseconds);
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function will be called when MRC is done.
+
+ @param PeiServices General purpose services available to every PEIM.
+
+ @param NotifyDescriptor Information about the notify event..
+
+ @param Ppi The notify context.
+
+ @retval EFI_SUCCESS If the function completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+MemoryDiscoveredPpiNotifyCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
+ UINT64 MemoryLength;
+ EFI_SMRAM_DESCRIPTOR *SmramDescriptor;
+ UINTN NumSmramRegions;
+ UINT32 RmuMainBaseAddress;
+ UINT32 RegData32;
+ UINT8 CpuAddressWidth;
+ UINT32 RegEax;
+ MTRR_SETTINGS MtrrSettings;
+
+ DEBUG ((EFI_D_INFO, "Platform PEIM Memory Callback\n"));
+
+ NumSmramRegions = 0;
+ SmramDescriptor = NULL;
+ RmuMainBaseAddress = 0;
+
+ PERF_START (NULL, "SetCache", NULL, 0);
+
+ InfoPostInstallMemory (&RmuMainBaseAddress, &SmramDescriptor, &NumSmramRegions);
+ ASSERT (SmramDescriptor != NULL);
+ ASSERT (RmuMainBaseAddress != 0);
+
+ MemoryLength = ((UINT64) RmuMainBaseAddress) + 0x10000;
+
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Get current MTRR settings
+ //
+ MtrrGetAllMtrrs (&MtrrSettings);
+
+ //
+ // Set all DRAM cachability to CacheWriteBack
+ //
+ Status = MtrrSetMemoryAttributeInMtrrSettings (&MtrrSettings, 0, MemoryLength, CacheWriteBack);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // RTC:28208 - System hang/crash when entering probe mode(ITP) when relocating SMBASE
+ // Workaround to make default SMRAM UnCachable
+ //
+ Status = MtrrSetMemoryAttributeInMtrrSettings (&MtrrSettings, 0x30000, SIZE_64KB, CacheUncacheable);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Set new MTRR settings
+ //
+ MtrrSetAllMtrrs (&MtrrSettings);
+
+ PERF_END (NULL, "SetCache", NULL, 0);
+
+ //
+ // Install PeiReset for PeiResetSystem service
+ //
+ Status = PeiServicesInstallPpi (&mPpiList[0]);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Do QNC initialization after MRC
+ //
+ PeiQNCPostMemInit ();
+
+ Status = PeiServicesInstallPpi (&mPpiStall[0]);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Set E000/F000 Routing
+ //
+ RegData32 = QNCPortRead (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC);
+ RegData32 |= (BIT2|BIT1);
+ QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC, RegData32);
+
+ if (BootMode == BOOT_IN_RECOVERY_MODE) {
+ Status = PeimInitializeRecovery (PeiServices);
+ ASSERT_EFI_ERROR (Status);
+ } else if (BootMode == BOOT_ON_S3_RESUME) {
+ return EFI_SUCCESS;
+ } else {
+ PeiServicesInstallFvInfoPpi (
+ NULL,
+ (VOID *) (UINTN) PcdGet32 (PcdFlashFvMainBase),
+ PcdGet32 (PcdFlashFvMainSize),
+ NULL,
+ NULL
+ );
+
+ //
+ // Publish the FVMAIN FV so the DXE Phase can dispatch drivers from this FV
+ // and produce Load File Protocols for UEFI Applications in this FV.
+ //
+ BuildFvHob (
+ PcdGet32 (PcdFlashFvMainBase),
+ PcdGet32 (PcdFlashFvMainSize)
+ );
+
+ //
+ // Publish the Payload FV so the DXE Phase can dispatch drivers from this FV
+ // and produce Load File Protocols for UEFI Applications in this FV.
+ //
+ BuildFvHob (
+ PcdGet32 (PcdFlashFvPayloadBase),
+ PcdGet32 (PcdFlashFvPayloadSize)
+ );
+ }
+
+ //
+ // Build flash HOB, it's going to be used by GCD and E820 building
+ // Map full SPI flash decode range (regardless of smaller SPI flash parts installed)
+ //
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_FIRMWARE_DEVICE,
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+ (SIZE_4GB - SIZE_8MB),
+ SIZE_8MB
+ );
+
+ //
+ // Create a CPU hand-off information
+ //
+ CpuAddressWidth = 32;
+ AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
+ if (RegEax >= CPUID_VIR_PHY_ADDRESS_SIZE) {
+ AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &RegEax, NULL, NULL, NULL);
+ CpuAddressWidth = (UINT8) (RegEax & 0xFF);
+ }
+ DEBUG ((EFI_D_INFO, "CpuAddressWidth: %d\n", CpuAddressWidth));
+
+ BuildCpuHob (CpuAddressWidth, 16);
+
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
diff --git a/QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.c b/QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.c new file mode 100644 index 0000000000..eee696e0e7 --- /dev/null +++ b/QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.c @@ -0,0 +1,1641 @@ +/** @file
+Framework PEIM to initialize memory on a Quark Memory Controller.
+
+Copyright (c) 2013 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CommonHeader.h"
+#include "MrcWrapper.h"
+#include <Ioh.h>
+#include "Platform.h"
+
+#include <Library/PlatformHelperLib.h>
+
+//
+// ------------------------ TSEG Base
+//
+// ------------------------ RESERVED_CPU_S3_SAVE_OFFSET
+// CPU S3 data
+// ------------------------ RESERVED_ACPI_S3_RANGE_OFFSET
+// S3 Memory base structure
+// ------------------------ TSEG + 1 page
+
+#define RESERVED_CPU_S3_SAVE_OFFSET (RESERVED_ACPI_S3_RANGE_OFFSET - sizeof (SMM_S3_RESUME_STATE))
+
+// Strap configuration register specifying DDR setup
+#define QUARK_SCSS_REG_STPDDRCFG 0x00
+
+// Macro counting array elements
+#define COUNT(a) (sizeof(a)/sizeof(*a))
+
+
+EFI_MEMORY_TYPE_INFORMATION mDefaultQncMemoryTypeInformation[] = {
+ { EfiReservedMemoryType, EDKII_RESERVED_SIZE_PAGES }, // BIOS Reserved
+ { EfiACPIMemoryNVS, ACPI_NVS_SIZE_PAGES }, // S3, SMM, etc
+ { EfiRuntimeServicesData, RUNTIME_SERVICES_DATA_SIZE_PAGES },
+ { EfiRuntimeServicesCode, RUNTIME_SERVICES_CODE_SIZE_PAGES },
+ { EfiACPIReclaimMemory, ACPI_RECLAIM_SIZE_PAGES }, // ACPI ASL
+ { EfiMaxMemoryType, 0 }
+};
+
+/**
+ Configure Uart mmio base for MRC serial log purpose
+
+ @param MrcData - MRC configuration data updated
+
+**/
+VOID
+MrcUartConfig(
+ MRC_PARAMS *MrcData
+ )
+{
+ UINT8 UartIdx;
+ UINT32 RegData32;
+ UINT8 IohUartBus;
+ UINT8 IohUartDev;
+
+ UartIdx = PcdGet8(PcdIohUartFunctionNumber);
+ IohUartBus = PcdGet8(PcdIohUartBusNumber);
+ IohUartDev = PcdGet8(PcdIohUartDevNumber);
+
+ RegData32 = PciRead32 (PCI_LIB_ADDRESS(IohUartBus, IohUartDev, UartIdx, PCI_BASE_ADDRESSREG_OFFSET));
+ MrcData->uart_mmio_base = RegData32 & 0xFFFFFFF0;
+}
+
+/**
+ Configure MRC from memory controller fuse settings.
+
+ @param MrcData - MRC configuration data to be updated.
+
+ @return EFI_SUCCESS MRC Config parameters updated from platform data.
+**/
+EFI_STATUS
+MrcConfigureFromMcFuses (
+ OUT MRC_PARAMS *MrcData
+ )
+{
+ UINT32 McFuseStat;
+
+ McFuseStat = QNCPortRead (
+ QUARK_NC_MEMORY_CONTROLLER_SB_PORT_ID,
+ QUARK_NC_MEMORY_CONTROLLER_REG_DFUSESTAT
+ );
+
+ DEBUG ((EFI_D_INFO, "MRC McFuseStat 0x%08x\n", McFuseStat));
+
+ if ((McFuseStat & B_DFUSESTAT_ECC_DIS) != 0) {
+ DEBUG ((EFI_D_INFO, "MRC Fuse : fus_dun_ecc_dis.\n"));
+ MrcData->ecc_enables = 0;
+ } else {
+ MrcData->ecc_enables = 1;
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Configure MRC from platform info hob.
+
+ @param MrcData - MRC configuration data to be updated.
+
+ @return EFI_SUCCESS MRC Config parameters updated from hob.
+ @return EFI_NOT_FOUND Platform Info or MRC Config parameters not found.
+ @return EFI_INVALID_PARAMETER Wrong params in hob.
+**/
+EFI_STATUS
+MrcConfigureFromInfoHob (
+ OUT MRC_PARAMS *MrcData
+ )
+{
+ PDAT_MRC_ITEM *ItemData;
+
+ ItemData = (PDAT_MRC_ITEM *)PcdGetPtr (PcdMrcParameters);
+
+ MrcData->channel_enables = ItemData->ChanMask;
+ MrcData->channel_width = ItemData->ChanWidth;
+ MrcData->address_mode = ItemData->AddrMode;
+ // Enable scrambling if requested.
+ MrcData->scrambling_enables = (ItemData->Flags & PDAT_MRC_FLAG_SCRAMBLE_EN) != 0;
+ MrcData->ddr_type = ItemData->DramType;
+ MrcData->dram_width = ItemData->DramWidth;
+ MrcData->ddr_speed = ItemData->DramSpeed;
+ // Enable ECC if requested.
+ MrcData->rank_enables = ItemData->RankMask;
+ MrcData->params.DENSITY = ItemData->DramDensity;
+ MrcData->params.tCL = ItemData->tCL;
+ MrcData->params.tRAS = ItemData->tRAS;
+ MrcData->params.tWTR = ItemData->tWTR;
+ MrcData->params.tRRD = ItemData->tRRD;
+ MrcData->params.tFAW = ItemData->tFAW;
+
+ MrcData->refresh_rate = ItemData->SrInt;
+ MrcData->sr_temp_range = ItemData->SrTemp;
+ MrcData->ron_value = ItemData->DramRonVal;
+ MrcData->rtt_nom_value = ItemData->DramRttNomVal;
+ MrcData->rd_odt_value = ItemData->SocRdOdtVal;
+
+ DEBUG ((EFI_D_INFO, "MRC dram_width %d\n", MrcData->dram_width));
+ DEBUG ((EFI_D_INFO, "MRC rank_enables %d\n",MrcData->rank_enables));
+ DEBUG ((EFI_D_INFO, "MRC ddr_speed %d\n", MrcData->ddr_speed));
+ DEBUG ((EFI_D_INFO, "MRC flags: %s\n",
+ (MrcData->scrambling_enables) ? L"SCRAMBLE_EN" : L""
+ ));
+
+ DEBUG ((EFI_D_INFO, "MRC density=%d tCL=%d tRAS=%d tWTR=%d tRRD=%d tFAW=%d\n",
+ MrcData->params.DENSITY,
+ MrcData->params.tCL,
+ MrcData->params.tRAS,
+ MrcData->params.tWTR,
+ MrcData->params.tRRD,
+ MrcData->params.tFAW
+ ));
+
+ return EFI_SUCCESS;
+}
+
+/**
+
+ Configure ECC scrub
+
+ @param MrcData - MRC configuration
+
+**/
+VOID
+EccScrubSetup(
+ const MRC_PARAMS *MrcData
+ )
+{
+ UINT32 BgnAdr = 0;
+ UINT32 EndAdr = MrcData->mem_size;
+ UINT32 BlkSize = PcdGet8(PcdEccScrubBlkSize) & SCRUB_CFG_BLOCKSIZE_MASK;
+ UINT32 Interval = PcdGet8(PcdEccScrubInterval) & SCRUB_CFG_INTERVAL_MASK;
+
+ if( MrcData->ecc_enables == 0 || MrcData->boot_mode == bmS3 || Interval == 0) {
+ // No scrub configuration needed if ECC not enabled
+ // On S3 resume reconfiguration is done as part of resume
+ // script, see SNCS3Save.c ==> SaveRuntimeScriptTable()
+ // Also if PCD disables scrub, then we do nothing.
+ return;
+ }
+
+ QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_END_MEM_REG, EndAdr);
+ QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_START_MEM_REG, BgnAdr);
+ QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_NEXT_READ_REG, BgnAdr);
+ QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_CONFIG_REG,
+ Interval << SCRUB_CFG_INTERVAL_SHIFT |
+ BlkSize << SCRUB_CFG_BLOCKSIZE_SHIFT);
+
+ McD0PciCfg32 (QNC_ACCESS_PORT_MCR) = SCRUB_RESUME_MSG();
+}
+
+/** Post InstallS3Memory / InstallEfiMemory tasks given MrcData context.
+
+ @param[in] MrcData MRC configuration.
+ @param[in] IsS3 TRUE if after InstallS3Memory.
+
+**/
+VOID
+PostInstallMemory (
+ IN MRC_PARAMS *MrcData,
+ IN BOOLEAN IsS3
+ )
+{
+ UINT32 RmuMainDestBaseAddress;
+ UINT32 *RmuMainSrcBaseAddress;
+ UINTN RmuMainSize;
+ EFI_STATUS Status;
+
+ //
+ // Setup ECC policy (All boot modes).
+ //
+ QNCPolicyDblEccBitErr (V_WDT_CONTROL_DBL_ECC_BIT_ERR_WARM);
+
+ //
+ // Find the 64KB of memory for Rmu Main at the top of available memory.
+ //
+ InfoPostInstallMemory (&RmuMainDestBaseAddress, NULL, NULL);
+ DEBUG ((EFI_D_INFO, "RmuMain Base Address : 0x%x\n", RmuMainDestBaseAddress));
+
+ //
+ // Relocate RmuMain.
+ //
+ if (IsS3) {
+ QNCSendOpcodeDramReady (RmuMainDestBaseAddress);
+ } else {
+ Status = PlatformFindFvFileRawDataSection (NULL, PcdGetPtr(PcdQuarkMicrocodeFile), (VOID **) &RmuMainSrcBaseAddress, &RmuMainSize);
+ ASSERT_EFI_ERROR (Status);
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_INFO, "Found Microcode ADDR:SIZE 0x%08x:0x%04x\n", (UINTN) RmuMainSrcBaseAddress, RmuMainSize));
+ }
+
+ RmuMainRelocation (RmuMainDestBaseAddress, (UINT32) RmuMainSrcBaseAddress, RmuMainSize);
+ QNCSendOpcodeDramReady (RmuMainDestBaseAddress);
+ EccScrubSetup (MrcData);
+ }
+}
+
+/**
+
+ Do memory initialisation for QNC DDR3 SDRAM Controller
+
+ @param FfsHeader Not used.
+ @param PeiServices General purpose services available to every PEIM.
+
+ @return EFI_SUCCESS Memory initialisation completed successfully.
+ All other error conditions encountered result in an ASSERT.
+
+**/
+EFI_STATUS
+MemoryInit (
+ IN EFI_PEI_SERVICES **PeiServices
+ )
+{
+ MRC_PARAMS MrcData;
+ EFI_BOOT_MODE BootMode;
+ EFI_STATUS Status;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
+ EFI_STATUS_CODE_VALUE ErrorCodeValue;
+ PEI_QNC_MEMORY_INIT_PPI *QncMemoryInitPpi;
+ UINT16 PmswAdr;
+
+ ErrorCodeValue = 0;
+
+ //
+ // It is critical that both of these data structures are initialized to 0.
+ // This PEIM knows the number of DIMMs in the system and works with that
+ // information. The MCH PEIM that consumes these data structures does not
+ // know the number of DIMMs so it expects the entire structure to be
+ // properly initialized. By initializing these to zero, all flags indicating
+ // that the SPD is present or the row should be configured are set to false.
+ //
+ ZeroMem (&MrcData, sizeof(MrcData));
+
+ //
+ // Get necessary PPI
+ //
+ Status = PeiServicesLocatePpi (
+ &gEfiPeiReadOnlyVariable2PpiGuid, // GUID
+ 0, // INSTANCE
+ NULL, // EFI_PEI_PPI_DESCRIPTOR
+ (VOID **)&VariableServices // PPI
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Determine boot mode
+ //
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Initialize Error type for reporting status code
+ //
+ switch (BootMode) {
+ case BOOT_ON_FLASH_UPDATE:
+ ErrorCodeValue = EFI_COMPUTING_UNIT_MEMORY + EFI_CU_MEMORY_EC_UPDATE_FAIL;
+ break;
+ case BOOT_ON_S3_RESUME:
+ ErrorCodeValue = EFI_COMPUTING_UNIT_MEMORY + EFI_CU_MEMORY_EC_S3_RESUME_FAIL;
+ break;
+ default:
+ ErrorCodeValue = EFI_COMPUTING_UNIT_MEMORY;
+ break;
+ }
+
+ //
+ // Specify MRC boot mode
+ //
+ switch (BootMode) {
+ case BOOT_ON_S3_RESUME:
+ case BOOT_ON_FLASH_UPDATE:
+ MrcData.boot_mode = bmS3;
+ break;
+ case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES:
+ MrcData.boot_mode = bmFast;
+ break;
+ default:
+ MrcData.boot_mode = bmCold;
+ break;
+ }
+
+ //
+ // Configure MRC input parameters.
+ //
+ Status = MrcConfigureFromMcFuses (&MrcData);
+ ASSERT_EFI_ERROR (Status);
+ Status = MrcConfigureFromInfoHob (&MrcData);
+ ASSERT_EFI_ERROR (Status);
+ MrcUartConfig(&MrcData);
+
+ if (BootMode == BOOT_IN_RECOVERY_MODE) {
+ //
+ // Always do bmCold on recovery.
+ //
+ DEBUG ((DEBUG_INFO, "MemoryInit:Force bmCold on Recovery\n"));
+ MrcData.boot_mode = bmCold;
+ } else {
+
+ //
+ // Load Memory configuration data saved in previous boot from variable
+ //
+ Status = LoadConfig (
+ PeiServices,
+ VariableServices,
+ &MrcData
+ );
+
+ if (EFI_ERROR (Status)) {
+
+ switch (BootMode) {
+ case BOOT_ON_S3_RESUME:
+ case BOOT_ON_FLASH_UPDATE:
+ REPORT_STATUS_CODE (
+ EFI_ERROR_CODE + EFI_ERROR_UNRECOVERED,
+ ErrorCodeValue
+ );
+ PeiServicesResetSystem ();
+ break;
+
+ default:
+ MrcData.boot_mode = bmCold;
+ break;
+ }
+ }
+ }
+
+ //
+ // Locate Memory Reference Code PPI
+ //
+ Status = PeiServicesLocatePpi (
+ &gQNCMemoryInitPpiGuid, // GUID
+ 0, // INSTANCE
+ NULL, // EFI_PEI_PPI_DESCRIPTOR
+ (VOID **)&QncMemoryInitPpi // PPI
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ PmswAdr = (UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_PMSW;
+ if( IoRead32 (PmswAdr) & B_QNC_GPE0BLK_PMSW_DRAM_INIT) {
+ // MRC did not complete last execution, force cold boot path
+ MrcData.boot_mode = bmCold;
+ }
+
+ // Mark MRC pending
+ IoOr32 (PmswAdr, (UINT32)B_QNC_GPE0BLK_PMSW_DRAM_INIT);
+
+ //
+ // Call Memory Reference Code's Routines
+ //
+ QncMemoryInitPpi->MrcStart (&MrcData);
+
+ // Mark MRC completed
+ IoAnd32 (PmswAdr, ~(UINT32)B_QNC_GPE0BLK_PMSW_DRAM_INIT);
+
+
+ //
+ // Note emulation platform has to read actual memory size
+ // MrcData.mem_size from PcdGet32 (PcdMemorySize);
+
+ if (BootMode == BOOT_ON_S3_RESUME) {
+
+ DEBUG ((EFI_D_INFO, "Following BOOT_ON_S3_RESUME boot path.\n"));
+
+ Status = InstallS3Memory (PeiServices, VariableServices, MrcData.mem_size);
+ if (EFI_ERROR (Status)) {
+ REPORT_STATUS_CODE (
+ EFI_ERROR_CODE + EFI_ERROR_UNRECOVERED,
+ ErrorCodeValue
+ );
+ PeiServicesResetSystem ();
+ }
+ PostInstallMemory (&MrcData, TRUE);
+ return EFI_SUCCESS;
+ }
+
+ //
+ // Assign physical memory to PEI and DXE
+ //
+ DEBUG ((EFI_D_INFO, "InstallEfiMemory.\n"));
+
+ Status = InstallEfiMemory (
+ PeiServices,
+ VariableServices,
+ BootMode,
+ MrcData.mem_size
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ PostInstallMemory (&MrcData, FALSE);
+
+ //
+ // Save current configuration into Hob and will save into Variable later in DXE
+ //
+ DEBUG ((EFI_D_INFO, "SaveConfig.\n"));
+ Status = SaveConfig (
+ &MrcData
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((EFI_D_INFO, "MemoryInit Complete.\n"));
+
+ return EFI_SUCCESS;
+}
+
+/**
+
+ This function saves a config to a HOB.
+
+ @param RowInfo The MCH row configuration information.
+ @param TimingData Timing data to be saved.
+ @param RowConfArray Row configuration information for each row in the system.
+ @param SpdData SPD info read for each DIMM slot in the system.
+
+ @return EFI_SUCCESS: The function completed successfully.
+
+**/
+EFI_STATUS
+SaveConfig (
+ IN MRC_PARAMS *MrcData
+ )
+{
+ //
+ // Build HOB data for Memory Config
+ // HOB data size (stored in variable) is required to be multiple of 8 bytes
+ //
+ BuildGuidDataHob (
+ &gEfiMemoryConfigDataGuid,
+ (VOID *) &MrcData->timings,
+ ((sizeof (MrcData->timings) + 0x7) & (~0x7))
+ );
+
+ DEBUG ((EFI_D_INFO, "IIO IoApicBase = %x IoApicLimit=%x\n", IOAPIC_BASE, (IOAPIC_BASE + IOAPIC_SIZE - 1)));
+ DEBUG ((EFI_D_INFO, "IIO RcbaAddress = %x\n", (UINT32)PcdGet64 (PcdRcbaMmioBaseAddress)));
+
+ return EFI_SUCCESS;
+}
+
+/**
+
+ Load a configuration stored in a variable.
+
+ @param TimingData Timing data to be loaded from NVRAM.
+ @param RowConfArray Row configuration information for each row in the system.
+
+ @return EFI_SUCCESS The function completed successfully.
+ Other Could not read variable.
+
+**/
+EFI_STATUS
+LoadConfig (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,
+ IN OUT MRC_PARAMS *MrcData
+ )
+{
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ PLATFORM_VARIABLE_MEMORY_CONFIG_DATA VarData;
+
+ BufferSize = ((sizeof (VarData.timings) + 0x7) & (~0x7)); // HOB data size (stored in variable) is required to be multiple of 8bytes
+
+ Status = VariableServices->GetVariable (
+ VariableServices,
+ EFI_MEMORY_CONFIG_DATA_NAME,
+ &gEfiMemoryConfigDataGuid,
+ NULL,
+ &BufferSize,
+ &VarData.timings
+ );
+ if (!EFI_ERROR (Status)) {
+ CopyMem (&MrcData->timings, &VarData.timings, sizeof(MrcData->timings));
+ }
+ return Status;
+}
+
+/**
+
+ This function installs memory.
+
+ @param PeiServices PEI Services table.
+ @param BootMode The specific boot path that is being followed
+ @param Mch Pointer to the DualChannelDdrMemoryInit PPI
+ @param RowConfArray Row configuration information for each row in the system.
+
+ @return EFI_SUCCESS The function completed successfully.
+ EFI_INVALID_PARAMETER One of the input parameters was invalid.
+ EFI_ABORTED An error occurred.
+
+**/
+EFI_STATUS
+InstallEfiMemory (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,
+ IN EFI_BOOT_MODE BootMode,
+ IN UINT32 TotalMemorySize
+ )
+{
+ EFI_PHYSICAL_ADDRESS PeiMemoryBaseAddress;
+ EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;
+ EFI_STATUS Status;
+ EFI_PEI_HOB_POINTERS Hob;
+ PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE MemoryMap[MAX_RANGES];
+ UINT8 Index;
+ UINT8 NumRanges;
+ UINT8 SmramIndex;
+ UINT8 SmramRanges;
+ UINT64 PeiMemoryLength;
+ UINTN BufferSize;
+ UINTN PeiMemoryIndex;
+ UINTN RequiredMemSize;
+ EFI_RESOURCE_ATTRIBUTE_TYPE Attribute;
+ EFI_PHYSICAL_ADDRESS BadMemoryAddress;
+ EFI_SMRAM_DESCRIPTOR DescriptorAcpiVariable;
+ VOID *CapsuleBuffer;
+ UINTN CapsuleBufferLength;
+ PEI_CAPSULE_PPI *Capsule;
+ VOID *LargeMemRangeBuf;
+ UINTN LargeMemRangeBufLen;
+
+ //
+ // Test the memory from 1M->TOM
+ //
+ if (BootMode != BOOT_ON_FLASH_UPDATE) {
+ Status = BaseMemoryTest (
+ PeiServices,
+ 0x100000,
+ (TotalMemorySize - 0x100000),
+ Quick,
+ &BadMemoryAddress
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+
+
+ //
+ // Get the Memory Map
+ //
+ NumRanges = MAX_RANGES;
+
+ ZeroMem (MemoryMap, sizeof (PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE) * NumRanges);
+
+ Status = GetMemoryMap (
+ PeiServices,
+ TotalMemorySize,
+ (PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *) MemoryMap,
+ &NumRanges
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Find the highest memory range in processor native address space to give to
+ // PEI. Then take the top.
+ //
+ PeiMemoryBaseAddress = 0;
+
+ //
+ // Query the platform for the minimum memory size
+ //
+
+ Status = GetPlatformMemorySize (
+ PeiServices,
+ BootMode,
+ &PeiMemoryLength
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Get required memory size for ACPI use. This helps to put ACPI memory on the topest
+ //
+ RequiredMemSize = 0;
+ RetriveRequiredMemorySize (PeiServices, &RequiredMemSize);
+
+ PeiMemoryIndex = 0;
+
+ for (Index = 0; Index < NumRanges; Index++)
+ {
+ DEBUG ((EFI_D_INFO, "Found 0x%x bytes at ", MemoryMap[Index].RangeLength));
+ DEBUG ((EFI_D_INFO, "0x%x.\n", MemoryMap[Index].PhysicalAddress));
+
+ if ((MemoryMap[Index].Type == DualChannelDdrMainMemory) &&
+ (MemoryMap[Index].PhysicalAddress + MemoryMap[Index].RangeLength < MAX_ADDRESS) &&
+ (MemoryMap[Index].PhysicalAddress >= PeiMemoryBaseAddress) &&
+ (MemoryMap[Index].RangeLength >= PeiMemoryLength)) {
+ PeiMemoryBaseAddress = MemoryMap[Index].PhysicalAddress +
+ MemoryMap[Index].RangeLength -
+ PeiMemoryLength;
+ PeiMemoryIndex = Index;
+ }
+ }
+
+ //
+ // Find the largest memory range excluding that given to PEI.
+ //
+ LargeMemRangeBuf = NULL;
+ LargeMemRangeBufLen = 0;
+ for (Index = 0; Index < NumRanges; Index++) {
+ if ((MemoryMap[Index].Type == DualChannelDdrMainMemory) &&
+ (MemoryMap[Index].PhysicalAddress + MemoryMap[Index].RangeLength < MAX_ADDRESS)) {
+ if (Index != PeiMemoryIndex) {
+ if (MemoryMap[Index].RangeLength > LargeMemRangeBufLen) {
+ LargeMemRangeBuf = (VOID *) ((UINTN) MemoryMap[Index].PhysicalAddress);
+ LargeMemRangeBufLen = (UINTN) MemoryMap[Index].RangeLength;
+ }
+ } else {
+ if ((MemoryMap[Index].RangeLength - PeiMemoryLength) >= LargeMemRangeBufLen) {
+ LargeMemRangeBuf = (VOID *) ((UINTN) MemoryMap[Index].PhysicalAddress);
+ LargeMemRangeBufLen = (UINTN) (MemoryMap[Index].RangeLength - PeiMemoryLength);
+ }
+ }
+ }
+ }
+
+ Capsule = NULL;
+ CapsuleBuffer = NULL;
+ CapsuleBufferLength = 0;
+ if (BootMode == BOOT_ON_FLASH_UPDATE) {
+ Status = PeiServicesLocatePpi (
+ &gPeiCapsulePpiGuid, // GUID
+ 0, // INSTANCE
+ NULL, // EFI_PEI_PPI_DESCRIPTOR
+ (VOID **)&Capsule // PPI
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (Status == EFI_SUCCESS) {
+ CapsuleBuffer = LargeMemRangeBuf;
+ CapsuleBufferLength = LargeMemRangeBufLen;
+
+ //
+ // Call the Capsule PPI Coalesce function to coalesce the capsule data.
+ //
+ Status = Capsule->Coalesce (
+ PeiServices,
+ &CapsuleBuffer,
+ &CapsuleBufferLength
+ );
+ //
+ // If it failed, then NULL out our capsule PPI pointer so that the capsule
+ // HOB does not get created below.
+ //
+ if (Status != EFI_SUCCESS) {
+ Capsule = NULL;
+ }
+ }
+ }
+
+ //
+ // Set up the IMR policy required for this platform
+ //
+ Status = SetPlatformImrPolicy (
+ PeiMemoryBaseAddress,
+ PeiMemoryLength,
+ RequiredMemSize
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Carve out the top memory reserved for ACPI
+ //
+ Status = PeiServicesInstallPeiMemory (PeiMemoryBaseAddress, (PeiMemoryLength - RequiredMemSize));
+ ASSERT_EFI_ERROR (Status);
+
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY, // MemoryType,
+ (
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_TESTED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
+ ),
+ PeiMemoryBaseAddress, // MemoryBegin
+ PeiMemoryLength // MemoryLength
+ );
+
+ //
+ // Install physical memory descriptor hobs for each memory range.
+ //
+ SmramRanges = 0;
+ for (Index = 0; Index < NumRanges; Index++) {
+ Attribute = 0;
+ if (MemoryMap[Index].Type == DualChannelDdrMainMemory)
+ {
+ if (Index == PeiMemoryIndex) {
+ //
+ // This is a partially tested Main Memory range, give it to EFI
+ //
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ (
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
+ ),
+ MemoryMap[Index].PhysicalAddress,
+ MemoryMap[Index].RangeLength - PeiMemoryLength
+ );
+ } else {
+ //
+ // This is an untested Main Memory range, give it to EFI
+ //
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY, // MemoryType,
+ (
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
+ ),
+ MemoryMap[Index].PhysicalAddress, // MemoryBegin
+ MemoryMap[Index].RangeLength // MemoryLength
+ );
+ }
+ } else {
+ if ((MemoryMap[Index].Type == DualChannelDdrSmramCacheable) ||
+ (MemoryMap[Index].Type == DualChannelDdrSmramNonCacheable)) {
+ SmramRanges++;
+ }
+ if ((MemoryMap[Index].Type == DualChannelDdrSmramNonCacheable) ||
+ (MemoryMap[Index].Type == DualChannelDdrGraphicsMemoryNonCacheable)) {
+ Attribute |= EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE;
+ }
+ if ((MemoryMap[Index].Type == DualChannelDdrSmramCacheable) ||
+ (MemoryMap[Index].Type == DualChannelDdrGraphicsMemoryCacheable)) {
+ //
+ // TSEG and HSEG can be used with a write-back(WB) cache policy; however,
+ // the specification requires that the TSEG and HSEG space be cached only
+ // inside of the SMI handler. when using HSEG or TSEG an IA-32 processor
+ // does not automatically write back and invalidate its cache before entering
+ // SMM or before existing SMM therefore any MTRR defined for the active TSEG
+ // or HSEG must be set to un-cacheable(UC) outside of SMM.
+ //
+ Attribute |= EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE;
+ }
+ if (MemoryMap[Index].Type == DualChannelDdrReservedMemory) {
+ Attribute |= EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE;
+ }
+ //
+ // Make sure non-system memory is marked as reserved
+ //
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_RESERVED, // MemoryType,
+ Attribute, // MemoryAttribute
+ MemoryMap[Index].PhysicalAddress, // MemoryBegin
+ MemoryMap[Index].RangeLength // MemoryLength
+ );
+ }
+ }
+
+ //
+ // Allocate one extra EFI_SMRAM_DESCRIPTOR to describe a page of SMRAM memory that contains a pointer
+ // to the SMM Services Table that is required on the S3 resume path
+ //
+ ASSERT (SmramRanges > 0);
+ BufferSize = sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK);
+ BufferSize += ((SmramRanges - 1) * sizeof (EFI_SMRAM_DESCRIPTOR));
+
+ Hob.Raw = BuildGuidHob (
+ &gEfiSmmPeiSmramMemoryReserveGuid,
+ BufferSize
+ );
+ ASSERT (Hob.Raw);
+
+ SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Hob.Raw);
+ SmramHobDescriptorBlock->NumberOfSmmReservedRegions = SmramRanges;
+
+ SmramIndex = 0;
+ for (Index = 0; Index < NumRanges; Index++) {
+ if ((MemoryMap[Index].Type == DualChannelDdrSmramCacheable) ||
+ (MemoryMap[Index].Type == DualChannelDdrSmramNonCacheable)
+ ) {
+ //
+ // This is an SMRAM range, create an SMRAM descriptor
+ //
+ SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalStart = MemoryMap[Index].PhysicalAddress;
+ SmramHobDescriptorBlock->Descriptor[SmramIndex].CpuStart = MemoryMap[Index].CpuAddress;
+ SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalSize = MemoryMap[Index].RangeLength;
+ if (MemoryMap[Index].Type == DualChannelDdrSmramCacheable) {
+ SmramHobDescriptorBlock->Descriptor[SmramIndex].RegionState = EFI_SMRAM_CLOSED | EFI_CACHEABLE;
+ } else {
+ SmramHobDescriptorBlock->Descriptor[SmramIndex].RegionState = EFI_SMRAM_CLOSED;
+ }
+
+ SmramIndex++;
+ }
+ }
+
+ //
+ // Build a HOB with the location of the reserved memory range.
+ //
+ CopyMem(&DescriptorAcpiVariable, &SmramHobDescriptorBlock->Descriptor[SmramRanges-1], sizeof(EFI_SMRAM_DESCRIPTOR));
+ DescriptorAcpiVariable.CpuStart += RESERVED_CPU_S3_SAVE_OFFSET;
+ BuildGuidDataHob (
+ &gEfiAcpiVariableGuid,
+ &DescriptorAcpiVariable,
+ sizeof (EFI_SMRAM_DESCRIPTOR)
+ );
+
+ //
+ // If we found the capsule PPI (and we didn't have errors), then
+ // call the capsule PEIM to allocate memory for the capsule.
+ //
+ if (Capsule != NULL) {
+ Status = Capsule->CreateState (PeiServices, CapsuleBuffer, CapsuleBufferLength);
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+
+ Find memory that is reserved so PEI has some to use.
+
+ @param PeiServices PEI Services table.
+ @param VariableSevices Variable PPI instance.
+
+ @return EFI_SUCCESS The function completed successfully.
+ Error value from LocatePpi()
+ Error Value from VariableServices->GetVariable()
+
+**/
+EFI_STATUS
+InstallS3Memory (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,
+ IN UINT32 TotalMemorySize
+ )
+{
+ EFI_STATUS Status;
+ UINTN S3MemoryBase;
+ UINTN S3MemorySize;
+ UINT8 SmramRanges;
+ UINT8 NumRanges;
+ UINT8 Index;
+ UINT8 SmramIndex;
+ UINTN BufferSize;
+ EFI_PEI_HOB_POINTERS Hob;
+ EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;
+ PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE MemoryMap[MAX_RANGES];
+ RESERVED_ACPI_S3_RANGE *S3MemoryRangeData;
+ EFI_SMRAM_DESCRIPTOR DescriptorAcpiVariable;
+
+ //
+ // Get the Memory Map
+ //
+ NumRanges = MAX_RANGES;
+
+ ZeroMem (MemoryMap, sizeof (PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE) * NumRanges);
+
+ Status = GetMemoryMap (
+ PeiServices,
+ TotalMemorySize,
+ (PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *) MemoryMap,
+ &NumRanges
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Install physical memory descriptor hobs for each memory range.
+ //
+ SmramRanges = 0;
+ for (Index = 0; Index < NumRanges; Index++) {
+ if ((MemoryMap[Index].Type == DualChannelDdrSmramCacheable) ||
+ (MemoryMap[Index].Type == DualChannelDdrSmramNonCacheable)) {
+ SmramRanges++;
+ }
+ }
+
+ ASSERT (SmramRanges > 0);
+
+ //
+ // Allocate one extra EFI_SMRAM_DESCRIPTOR to describe a page of SMRAM memory that contains a pointer
+ // to the SMM Services Table that is required on the S3 resume path
+ //
+ BufferSize = sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK);
+ if (SmramRanges > 0) {
+ BufferSize += ((SmramRanges - 1) * sizeof (EFI_SMRAM_DESCRIPTOR));
+ }
+
+ Hob.Raw = BuildGuidHob (
+ &gEfiSmmPeiSmramMemoryReserveGuid,
+ BufferSize
+ );
+ ASSERT (Hob.Raw);
+
+ SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Hob.Raw);
+ SmramHobDescriptorBlock->NumberOfSmmReservedRegions = SmramRanges;
+
+ SmramIndex = 0;
+ for (Index = 0; Index < NumRanges; Index++) {
+ if ((MemoryMap[Index].Type == DualChannelDdrSmramCacheable) ||
+ (MemoryMap[Index].Type == DualChannelDdrSmramNonCacheable)
+ ) {
+ //
+ // This is an SMRAM range, create an SMRAM descriptor
+ //
+ SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalStart = MemoryMap[Index].PhysicalAddress;
+ SmramHobDescriptorBlock->Descriptor[SmramIndex].CpuStart = MemoryMap[Index].CpuAddress;
+ SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalSize = MemoryMap[Index].RangeLength;
+ if (MemoryMap[Index].Type == DualChannelDdrSmramCacheable) {
+ SmramHobDescriptorBlock->Descriptor[SmramIndex].RegionState = EFI_SMRAM_CLOSED | EFI_CACHEABLE;
+ } else {
+ SmramHobDescriptorBlock->Descriptor[SmramIndex].RegionState = EFI_SMRAM_CLOSED;
+ }
+
+ SmramIndex++;
+ }
+ }
+
+ //
+ // Build a HOB with the location of the reserved memory range.
+ //
+ CopyMem(&DescriptorAcpiVariable, &SmramHobDescriptorBlock->Descriptor[SmramRanges-1], sizeof(EFI_SMRAM_DESCRIPTOR));
+ DescriptorAcpiVariable.CpuStart += RESERVED_CPU_S3_SAVE_OFFSET;
+ BuildGuidDataHob (
+ &gEfiAcpiVariableGuid,
+ &DescriptorAcpiVariable,
+ sizeof (EFI_SMRAM_DESCRIPTOR)
+ );
+
+ //
+ // Get the location and size of the S3 memory range in the reserved page and
+ // install it as PEI Memory.
+ //
+
+ DEBUG ((EFI_D_INFO, "TSEG Base = 0x%08x\n", SmramHobDescriptorBlock->Descriptor[SmramRanges-1].PhysicalStart));
+ S3MemoryRangeData = (RESERVED_ACPI_S3_RANGE*)(UINTN)
+ (SmramHobDescriptorBlock->Descriptor[SmramRanges-1].PhysicalStart + RESERVED_ACPI_S3_RANGE_OFFSET);
+
+ S3MemoryBase = (UINTN) (S3MemoryRangeData->AcpiReservedMemoryBase);
+ DEBUG ((EFI_D_INFO, "S3MemoryBase = 0x%08x\n", S3MemoryBase));
+ S3MemorySize = (UINTN) (S3MemoryRangeData->AcpiReservedMemorySize);
+ DEBUG ((EFI_D_INFO, "S3MemorySize = 0x%08x\n", S3MemorySize));
+
+ Status = PeiServicesInstallPeiMemory (S3MemoryBase, S3MemorySize);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Retrieve the system memory length and build memory hob for the system
+ // memory above 1MB. So Memory Callback can set cache for the system memory
+ // correctly on S3 boot path, just like it does on Normal boot path.
+ //
+ ASSERT_EFI_ERROR ((S3MemoryRangeData->SystemMemoryLength - 0x100000) > 0);
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ (
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
+ ),
+ 0x100000,
+ S3MemoryRangeData->SystemMemoryLength - 0x100000
+ );
+
+ for (Index = 0; Index < NumRanges; Index++) {
+ if ((MemoryMap[Index].Type == DualChannelDdrMainMemory) &&
+ (MemoryMap[Index].PhysicalAddress + MemoryMap[Index].RangeLength < 0x100000)) {
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ (
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
+ ),
+ MemoryMap[Index].PhysicalAddress,
+ MemoryMap[Index].RangeLength
+ );
+ DEBUG ((EFI_D_INFO, "Build resource HOB for Legacy Region on S3 patch :"));
+ DEBUG ((EFI_D_INFO, " Memory Base:0x%lX Length:0x%lX\n", MemoryMap[Index].PhysicalAddress, MemoryMap[Index].RangeLength));
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+
+ This function returns the size, in bytes, required for the DXE phase.
+
+ @param PeiServices PEI Services table.
+ @param Size Pointer to the size, in bytes, required for the DXE phase.
+
+ @return None
+
+**/
+VOID
+RetriveRequiredMemorySize (
+ IN EFI_PEI_SERVICES **PeiServices,
+ OUT UINTN *Size
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_HOB_POINTERS Hob;
+ EFI_MEMORY_TYPE_INFORMATION *MemoryData;
+ UINT8 Index;
+ UINTN TempPageNum;
+
+ MemoryData = NULL;
+ TempPageNum = 0;
+ Index = 0;
+
+ Status = PeiServicesGetHobList ((VOID **)&Hob.Raw);
+ while (!END_OF_HOB_LIST (Hob)) {
+ if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION &&
+ CompareGuid (&Hob.Guid->Name, &gEfiMemoryTypeInformationGuid)
+ ) {
+ MemoryData = (EFI_MEMORY_TYPE_INFORMATION *) (Hob.Raw + sizeof (EFI_HOB_GENERIC_HEADER) + sizeof (EFI_GUID));
+ break;
+ }
+
+ Hob.Raw = GET_NEXT_HOB (Hob);
+ }
+ //
+ // Platform PEIM should supply such a information. Generic PEIM doesn't assume any default value
+ //
+ if (!MemoryData) {
+ return ;
+ }
+
+ while (MemoryData[Index].Type != EfiMaxMemoryType) {
+ //
+ // Accumulate default memory size requirements
+ //
+ TempPageNum += MemoryData[Index].NumberOfPages;
+ Index++;
+ }
+
+ if (TempPageNum == 0) {
+ return ;
+ }
+
+ //
+ // Add additional pages used by DXE memory manager
+ //
+ (*Size) = (TempPageNum + EDKII_DXE_MEM_SIZE_PAGES) * EFI_PAGE_SIZE;
+
+ return ;
+}
+
+/**
+
+ This function returns the memory ranges to be enabled, along with information
+ describing how the range should be used.
+
+ @param PeiServices PEI Services Table.
+ @param TimingData Detected DDR timing parameters for installed memory.
+ @param RowConfArray Pointer to an array of EFI_DUAL_CHANNEL_DDR_ROW_CONFIG structures. The number
+ of items in the array must match MaxRows returned by the McGetRowInfo() function.
+ @param MemoryMap Buffer to record details of the memory ranges tobe enabled.
+ @param NumRanges On input, this contains the maximum number of memory ranges that can be described
+ in the MemoryMap buffer.
+
+ @return MemoryMap The buffer will be filled in
+ NumRanges will contain the actual number of memory ranges that are to be anabled.
+ EFI_SUCCESS The function completed successfully.
+
+**/
+EFI_STATUS
+GetMemoryMap (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN UINT32 TotalMemorySize,
+ IN OUT PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *MemoryMap,
+ IN OUT UINT8 *NumRanges
+ )
+{
+ EFI_PHYSICAL_ADDRESS MemorySize;
+ EFI_PHYSICAL_ADDRESS RowLength;
+ EFI_STATUS Status;
+ PEI_MEMORY_RANGE_PCI_MEMORY PciMemoryMask;
+ PEI_MEMORY_RANGE_OPTION_ROM OptionRomMask;
+ PEI_MEMORY_RANGE_SMRAM SmramMask;
+ PEI_MEMORY_RANGE_SMRAM TsegMask;
+ UINT32 BlockNum;
+ UINT8 EsmramcRegister;
+ UINT8 ExtendedMemoryIndex;
+ UINT32 Register;
+
+ if ((*NumRanges) < MAX_RANGES) {
+ return EFI_BUFFER_TOO_SMALL;
+ }
+
+ *NumRanges = 0;
+
+ //
+ // Find out which memory ranges to reserve on this platform
+ //
+ Status = ChooseRanges (
+ &OptionRomMask,
+ &SmramMask,
+ &PciMemoryMask
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Generate Memory ranges for the memory map.
+ //
+ EsmramcRegister = 0;
+ MemorySize = 0;
+
+ RowLength = TotalMemorySize;
+
+ //
+ // Add memory below 640KB to the memory map. Make sure memory between
+ // 640KB and 1MB are reserved, even if not used for SMRAM
+ //
+ MemoryMap[*NumRanges].PhysicalAddress = MemorySize;
+ MemoryMap[*NumRanges].CpuAddress = MemorySize;
+ MemoryMap[*NumRanges].RangeLength = 0xA0000;
+ MemoryMap[*NumRanges].Type = DualChannelDdrMainMemory;
+ (*NumRanges)++;
+
+ //
+ // Just mark this range reserved
+ //
+ MemoryMap[*NumRanges].PhysicalAddress = 0xA0000;
+ MemoryMap[*NumRanges].CpuAddress = 0xA0000;
+ MemoryMap[*NumRanges].RangeLength = 0x60000;
+ MemoryMap[*NumRanges].Type = DualChannelDdrReservedMemory;
+ (*NumRanges)++;
+
+ RowLength -= (0x100000 - MemorySize);
+ MemorySize = 0x100000;
+
+ //
+ // Add remaining memory to the memory map
+ //
+ MemoryMap[*NumRanges].PhysicalAddress = MemorySize;
+ MemoryMap[*NumRanges].CpuAddress = MemorySize;
+ MemoryMap[*NumRanges].RangeLength = RowLength;
+ MemoryMap[*NumRanges].Type = DualChannelDdrMainMemory;
+ (*NumRanges)++;
+ MemorySize += RowLength;
+
+ ExtendedMemoryIndex = (UINT8) (*NumRanges - 1);
+
+ // See if we need to trim TSEG out of the highest memory range
+ //
+ if (SmramMask & PEI_MR_SMRAM_TSEG_MASK) {//pcd
+ //
+ // Create the new range for TSEG and remove that range from the previous SdrDdrMainMemory range
+ //
+ TsegMask = (SmramMask & PEI_MR_SMRAM_SIZE_MASK);
+
+ BlockNum = 1;
+ while (TsegMask) {
+ TsegMask >>= 1;
+ BlockNum <<= 1;
+ }
+
+ BlockNum >>= 1;
+
+ if (BlockNum) {
+
+ MemoryMap[*NumRanges].RangeLength = (BlockNum * 128 * 1024);
+ Register = (UINT32)((MemorySize - 1) & SMM_END_MASK);
+ MemorySize -= MemoryMap[*NumRanges].RangeLength;
+ MemoryMap[*NumRanges].PhysicalAddress = MemorySize;
+ MemoryMap[*NumRanges].CpuAddress = MemorySize;
+ MemoryMap[ExtendedMemoryIndex].RangeLength -= MemoryMap[*NumRanges].RangeLength;
+
+ //
+ // Update QuarkNcSoc HSMMCTL register
+ //
+ Register |= (UINT32)(((RShiftU64(MemorySize, 16)) & SMM_START_MASK) + (SMM_WRITE_OPEN | SMM_READ_OPEN | SMM_CODE_RD_OPEN));
+ QncHsmmcWrite (Register);
+ }
+
+ //
+ // Chipset only supports cacheable SMRAM
+ //
+ MemoryMap[*NumRanges].Type = DualChannelDdrSmramCacheable;
+
+ (*NumRanges)++;
+ }
+
+ //
+ // trim 64K memory from highest memory range for Rmu Main binary shadow
+ //
+ MemoryMap[*NumRanges].RangeLength = 0x10000;
+ MemorySize -= MemoryMap[*NumRanges].RangeLength;
+ MemoryMap[*NumRanges].PhysicalAddress = MemorySize;
+ MemoryMap[*NumRanges].CpuAddress = MemorySize;
+ MemoryMap[ExtendedMemoryIndex].RangeLength -= MemoryMap[*NumRanges].RangeLength;
+ MemoryMap[*NumRanges].Type = DualChannelDdrReservedMemory;
+ (*NumRanges)++;
+
+ return EFI_SUCCESS;
+}
+
+/**
+
+Routine Description:
+
+ Fill in bit masks to specify reserved memory ranges on the Lakeport platform
+
+Arguments:
+
+Returns:
+
+ OptionRomMask - Bit mask specifying memory regions reserved for Legacy option
+ ROM use (if any)
+
+ SmramMask - Bit mask specifying memory regions reserved for SMM use (if any)
+
+**/
+EFI_STATUS
+ChooseRanges (
+ IN OUT PEI_MEMORY_RANGE_OPTION_ROM *OptionRomMask,
+ IN OUT PEI_MEMORY_RANGE_SMRAM *SmramMask,
+ IN OUT PEI_MEMORY_RANGE_PCI_MEMORY *PciMemoryMask
+ )
+{
+
+ //
+ // Choose regions to reserve for Option ROM use
+ //
+ *OptionRomMask = PEI_MR_OPTION_ROM_NONE;
+
+ //
+ // Choose regions to reserve for SMM use (AB/H SEG and TSEG). Size is in 128K blocks
+ //
+ *SmramMask = PEI_MR_SMRAM_CACHEABLE_MASK | PEI_MR_SMRAM_TSEG_MASK | ((PcdGet32(PcdTSegSize)) >> 17);
+
+ *PciMemoryMask = 0;
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+GetPlatformMemorySize (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_BOOT_MODE BootMode,
+ IN OUT UINT64 *MemorySize
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
+ UINTN DataSize;
+ EFI_MEMORY_TYPE_INFORMATION MemoryData [EfiMaxMemoryType + 1];
+ UINTN Index;
+
+ DataSize = sizeof (MemoryData);
+
+ if (BootMode == BOOT_IN_RECOVERY_MODE) {
+
+ //
+ // // Treat recovery as if variable not found (eg 1st boot).
+ //
+ Status = EFI_NOT_FOUND;
+
+ } else {
+ Status = PeiServicesLocatePpi (
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ 0,
+ NULL,
+ (VOID **)&Variable
+ );
+
+ ASSERT_EFI_ERROR (Status);
+
+ DataSize = sizeof (MemoryData);
+ Status = Variable->GetVariable (
+ Variable,
+ EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
+ &gEfiMemoryTypeInformationGuid,
+ NULL,
+ &DataSize,
+ &MemoryData
+ );
+ }
+
+ //
+ // Accumulate maximum amount of memory needed
+ //
+ if (EFI_ERROR (Status)) {
+ //
+ // Start with minimum memory
+ //
+ *MemorySize = PEI_MIN_MEMORY_SIZE;
+
+ for (Index = 0; Index < sizeof(mDefaultQncMemoryTypeInformation) / sizeof (EFI_MEMORY_TYPE_INFORMATION); Index++) {
+ *MemorySize += mDefaultQncMemoryTypeInformation[Index].NumberOfPages * EFI_PAGE_SIZE;
+ }
+
+ //
+ // Build the GUID'd HOB for DXE
+ //
+ BuildGuidDataHob (
+ &gEfiMemoryTypeInformationGuid,
+ mDefaultQncMemoryTypeInformation,
+ sizeof(mDefaultQncMemoryTypeInformation)
+ );
+ } else {
+ //
+ // Start with at least PEI_MIN_MEMORY_SIZE pages of memory for the DXE Core and the DXE Stack
+ //
+
+ *MemorySize = PEI_MIN_MEMORY_SIZE;
+ for (Index = 0; Index < DataSize / sizeof (EFI_MEMORY_TYPE_INFORMATION); Index++) {
+ DEBUG ((EFI_D_INFO, "Index %d, Page: %d\n", Index, MemoryData[Index].NumberOfPages));
+ *MemorySize += MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE;
+ }
+
+ //
+ // Build the GUID'd HOB for DXE
+ //
+ BuildGuidDataHob (
+ &gEfiMemoryTypeInformationGuid,
+ MemoryData,
+ DataSize
+ );
+
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+BaseMemoryTest (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PHYSICAL_ADDRESS BeginAddress,
+ IN UINT64 MemoryLength,
+ IN PEI_MEMORY_TEST_OP Operation,
+ OUT EFI_PHYSICAL_ADDRESS *ErrorAddress
+ )
+{
+ UINT32 TestPattern;
+ EFI_PHYSICAL_ADDRESS TempAddress;
+ UINT32 SpanSize;
+
+ TestPattern = 0x5A5A5A5A;
+ SpanSize = 0;
+
+ //
+ // Make sure we don't try and test anything above the max physical address range
+ //
+ ASSERT (BeginAddress + MemoryLength < MAX_ADDRESS);
+
+ switch (Operation) {
+ case Extensive:
+ SpanSize = 0x4;
+ break;
+
+ case Sparse:
+ case Quick:
+ SpanSize = 0x40000;
+ break;
+
+ case Ignore:
+ goto Done;
+ break;
+ }
+ //
+ // Write the test pattern into memory range
+ //
+ TempAddress = BeginAddress;
+ while (TempAddress < BeginAddress + MemoryLength) {
+ (*(UINT32 *) (UINTN) TempAddress) = TestPattern;
+ TempAddress += SpanSize;
+ }
+ //
+ // Read pattern from memory and compare it
+ //
+ TempAddress = BeginAddress;
+ while (TempAddress < BeginAddress + MemoryLength) {
+ if ((*(UINT32 *) (UINTN) TempAddress) != TestPattern) {
+ *ErrorAddress = TempAddress;
+ DEBUG ((EFI_D_ERROR, "Memory test failed at 0x%x.\n", TempAddress));
+ return EFI_DEVICE_ERROR;
+ }
+
+ TempAddress += SpanSize;
+ }
+
+Done:
+ return EFI_SUCCESS;
+}
+
+/**
+
+ This function sets up the platform specific IMR protection for the various
+ memory regions.
+
+ @param PeiMemoryBaseAddress Base address of memory allocated for PEI.
+ @param PeiMemoryLength Length in bytes of the PEI memory (includes ACPI memory).
+ @param RequiredMemSize Size in bytes of the ACPI/Runtime memory
+
+ @return EFI_SUCCESS The function completed successfully.
+ EFI_ACCESS_DENIED Access to IMRs failed.
+
+**/
+EFI_STATUS
+SetPlatformImrPolicy (
+ IN EFI_PHYSICAL_ADDRESS PeiMemoryBaseAddress,
+ IN UINT64 PeiMemoryLength,
+ IN UINTN RequiredMemSize
+ )
+{
+ UINT8 Index;
+ UINT32 Register;
+ UINT16 DeviceId;
+
+ //
+ // Check what Soc we are running on (read Host bridge DeviceId)
+ //
+ DeviceId = QNCMmPci16(0, MC_BUS, MC_DEV, MC_FUN, PCI_DEVICE_ID_OFFSET);
+
+ //
+ // If any IMR register is locked then we cannot proceed
+ //
+ for (Index = (QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXL); Index <=(QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXL); Index=Index+4)
+ {
+ Register = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, Index);
+ if (Register & IMR_LOCK) {
+ return EFI_ACCESS_DENIED;
+ }
+ }
+
+ //
+ // Add IMR0 protection for the 'PeiMemory'
+ //
+ QncImrWrite (
+ QUARK_NC_MEMORY_MANAGER_IMR0,
+ (UINT32)(((RShiftU64(PeiMemoryBaseAddress, 8)) & IMRL_MASK) | IMR_EN),
+ (UINT32)((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength-RequiredMemSize + EFI_PAGES_TO_SIZE(EDKII_DXE_MEM_SIZE_PAGES-1) - 1), 8)) & IMRL_MASK),
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM),
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM)
+ );
+
+ //
+ // Add IMR2 protection for shadowed RMU binary.
+ //
+ QncImrWrite (
+ QUARK_NC_MEMORY_MANAGER_IMR2,
+ (UINT32)(((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength), 8)) & IMRH_MASK) | IMR_EN),
+ (UINT32)((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength+PcdGet32(PcdFlashQNCMicrocodeSize)-1), 8)) & IMRH_MASK),
+ (UINT32)(CPU_SNOOP + RMU + CPU0_NON_SMM),
+ (UINT32)(CPU_SNOOP + RMU + CPU0_NON_SMM)
+ );
+
+ //
+ // Add IMR3 protection for the default SMRAM.
+ //
+ QncImrWrite (
+ QUARK_NC_MEMORY_MANAGER_IMR3,
+ (UINT32)(((RShiftU64((SMM_DEFAULT_SMBASE), 8)) & IMRL_MASK) | IMR_EN),
+ (UINT32)((RShiftU64((SMM_DEFAULT_SMBASE+SMM_DEFAULT_SMBASE_SIZE_BYTES-1), 8)) & IMRH_MASK),
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM),
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM)
+ );
+
+ //
+ // Add IMR5 protection for the legacy S3 and AP Startup Vector region (below 1MB).
+ //
+ QncImrWrite (
+ QUARK_NC_MEMORY_MANAGER_IMR5,
+ (UINT32)(((RShiftU64(AP_STARTUP_VECTOR, 8)) & IMRL_MASK) | IMR_EN),
+ (UINT32)((RShiftU64((AP_STARTUP_VECTOR + EFI_PAGE_SIZE - 1), 8)) & IMRH_MASK),
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM),
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM)
+ );
+
+ //
+ // Add IMR6 protection for the ACPI Reclaim/ACPI/Runtime Services.
+ //
+ QncImrWrite (
+ QUARK_NC_MEMORY_MANAGER_IMR6,
+ (UINT32)(((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength-RequiredMemSize+EFI_PAGES_TO_SIZE(EDKII_DXE_MEM_SIZE_PAGES-1)), 8)) & IMRL_MASK) | IMR_EN),
+ (UINT32)((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength-EFI_PAGE_SIZE-1), 8)) & IMRH_MASK),
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM),
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM)
+ );
+
+ //
+ // Enable IMR4 protection of eSRAM.
+ //
+ QncImrWrite (
+ QUARK_NC_MEMORY_MANAGER_IMR4,
+ (UINT32)(((RShiftU64((UINTN)PcdGet32 (PcdEsramStage1Base), 8)) & IMRL_MASK) | IMR_EN),
+ (UINT32)((RShiftU64(((UINTN)PcdGet32 (PcdEsramStage1Base) + (UINTN)PcdGet32 (PcdESramMemorySize) - 1), 8)) & IMRH_MASK),
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM),
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM)
+ );
+
+ //
+ // Enable Interrupt on IMR/SMM Violation
+ //
+ QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_BIMRVCTL, (UINT32)(EnableIMRInt));
+ if (DeviceId == QUARK2_MC_DEVICE_ID) {
+ QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_BSMMVCTL, (UINT32)(EnableSMMInt));
+ }
+
+ //
+ // Disable IMR7 memory protection (eSRAM + DDR3 memory) since our policies
+ // are now setup.
+ //
+ QncImrWrite (
+ QUARK_NC_MEMORY_MANAGER_IMR7,
+ (UINT32)(IMRL_RESET & ~IMR_EN),
+ (UINT32)IMRH_RESET,
+ (UINT32)IMRX_ALL_ACCESS,
+ (UINT32)IMRX_ALL_ACCESS
+ );
+
+ return EFI_SUCCESS;
+}
+
+/** Return info derived from Installing Memory by MemoryInit.
+
+ @param[out] RmuMainBaseAddressPtr Return RmuMainBaseAddress to this location.
+ @param[out] SmramDescriptorPtr Return start of Smram descriptor list to this location.
+ @param[out] NumSmramRegionsPtr Return numbers of Smram regions to this location.
+
+ @return Address of RMU shadow region at the top of available memory.
+ @return List of Smram descriptors for each Smram region.
+ @return Numbers of Smram regions.
+**/
+VOID
+EFIAPI
+InfoPostInstallMemory (
+ OUT UINT32 *RmuMainBaseAddressPtr OPTIONAL,
+ OUT EFI_SMRAM_DESCRIPTOR **SmramDescriptorPtr OPTIONAL,
+ OUT UINTN *NumSmramRegionsPtr OPTIONAL
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_HOB_POINTERS Hob;
+ UINT64 CalcLength;
+ EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;
+
+ if ((RmuMainBaseAddressPtr == NULL) && (SmramDescriptorPtr == NULL) && (NumSmramRegionsPtr == NULL)) {
+ return;
+ }
+
+ SmramHobDescriptorBlock = NULL;
+ if (SmramDescriptorPtr != NULL) {
+ *SmramDescriptorPtr = NULL;
+ }
+ if (NumSmramRegionsPtr != NULL) {
+ *NumSmramRegionsPtr = 0;
+ }
+
+ //
+ // Calculate RMU shadow region base address.
+ // Set to 1 MB. Since 1MB cacheability will always be set
+ // until override by CSM.
+ //
+ CalcLength = 0x100000;
+
+ Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
+ ASSERT_EFI_ERROR (Status);
+ while (!END_OF_HOB_LIST (Hob)) {
+ if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
+ if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {
+ //
+ // Skip the memory region below 1MB
+ //
+ if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) {
+ CalcLength += (UINT64) (Hob.ResourceDescriptor->ResourceLength);
+ }
+ }
+ } else if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION) {
+ if (CompareGuid (&(Hob.Guid->Name), &gEfiSmmPeiSmramMemoryReserveGuid)) {
+ SmramHobDescriptorBlock = (VOID*) (Hob.Raw + sizeof (EFI_HOB_GUID_TYPE));
+ if (SmramDescriptorPtr != NULL) {
+ *SmramDescriptorPtr = SmramHobDescriptorBlock->Descriptor;
+ }
+ if (NumSmramRegionsPtr != NULL) {
+ *NumSmramRegionsPtr = SmramHobDescriptorBlock->NumberOfSmmReservedRegions;
+ }
+ }
+ }
+ Hob.Raw = GET_NEXT_HOB (Hob);
+ }
+
+ if (RmuMainBaseAddressPtr != NULL) {
+ *RmuMainBaseAddressPtr = (UINT32) CalcLength;
+ }
+}
diff --git a/QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.h b/QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.h new file mode 100644 index 0000000000..e0f06a3b0e --- /dev/null +++ b/QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.h @@ -0,0 +1,240 @@ +/** @file
+Framework PEIM to initialize memory on an DDR2 SDRAM Memory Controller.
+
+Copyright (c) 2013 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MRC_WRAPPER_H
+#define _MRC_WRAPPER_H
+
+#include <Ppi/QNCMemoryInit.h>
+#include "PlatformEarlyInit.h"
+
+//
+// Define the default memory areas required
+//
+#define EDKII_RESERVED_SIZE_PAGES 0x40
+#define ACPI_NVS_SIZE_PAGES 0x40
+#define RUNTIME_SERVICES_DATA_SIZE_PAGES 0x20
+#define RUNTIME_SERVICES_CODE_SIZE_PAGES 0x60
+#define ACPI_RECLAIM_SIZE_PAGES 0x10
+#define EDKII_DXE_MEM_SIZE_PAGES 0x20
+
+#define AP_STARTUP_VECTOR 0x00097000
+
+//
+// Maximum number of "Socket Sets", where a "Socket Set is a set of matching
+// DIMM's from the various channels
+//
+#define MAX_SOCKET_SETS 2
+
+//
+// Maximum number of memory ranges supported by the memory controller
+//
+#define MAX_RANGES (MAX_ROWS + 5)
+
+//
+// Min. of 48MB PEI phase
+//
+#define PEI_MIN_MEMORY_SIZE (6 * 0x800000)
+#define PEI_RECOVERY_MIN_MEMORY_SIZE (6 * 0x800000)
+
+#define PEI_MEMORY_RANGE_OPTION_ROM UINT32
+#define PEI_MR_OPTION_ROM_NONE 0x00000000
+
+//
+// SMRAM Memory Range
+//
+#define PEI_MEMORY_RANGE_SMRAM UINT32
+#define PEI_MR_SMRAM_ALL 0xFFFFFFFF
+#define PEI_MR_SMRAM_NONE 0x00000000
+#define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000
+#define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000
+#define PEI_MR_SMRAM_ABSEG_MASK 0x00010000
+#define PEI_MR_SMRAM_HSEG_MASK 0x00020000
+#define PEI_MR_SMRAM_TSEG_MASK 0x00040000
+//
+// SMRAM Size is a multiple of 128KB.
+//
+#define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF
+
+//
+// Pci Memory Hole
+//
+#define PEI_MEMORY_RANGE_PCI_MEMORY UINT32
+
+typedef enum {
+ Ignore,
+ Quick,
+ Sparse,
+ Extensive
+} PEI_MEMORY_TEST_OP;
+
+//
+// MRC Params Variable structure.
+//
+
+typedef struct {
+ MrcTimings_t timings; // Actual MRC config values saved in variable store.
+ UINT8 VariableStorePad[8]; // Allow for data stored in variable is required to be multiple of 8bytes.
+} PLATFORM_VARIABLE_MEMORY_CONFIG_DATA;
+
+///
+/// MRC Params Platform Data Flags bits
+///
+#define PDAT_MRC_FLAG_ECC_EN BIT0
+#define PDAT_MRC_FLAG_SCRAMBLE_EN BIT1
+#define PDAT_MRC_FLAG_MEMTEST_EN BIT2
+#define PDAT_MRC_FLAG_TOP_TREE_EN BIT3 ///< 0b DDR "fly-by" topology else 1b DDR "tree" topology.
+#define PDAT_MRC_FLAG_WR_ODT_EN BIT4 ///< If set ODR signal is asserted to DRAM devices on writes.
+
+///
+/// MRC Params Platform Data.
+///
+typedef struct {
+ UINT32 Flags; ///< Bitmap of PDAT_MRC_FLAG_XXX defs above.
+ UINT8 DramWidth; ///< 0=x8, 1=x16, others=RESERVED.
+ UINT8 DramSpeed; ///< 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory.
+ UINT8 DramType; ///< 0=DDR3,1=DDR3L, others=RESERVED.
+ UINT8 RankMask; ///< bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED.
+ UINT8 ChanMask; ///< bit[0] CHAN0_EN, others=RESERVED.
+ UINT8 ChanWidth; ///< 1=x16, others=RESERVED.
+ UINT8 AddrMode; ///< 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED.
+ UINT8 SrInt; ///< 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE.
+ UINT8 SrTemp; ///< 0=normal, 1=extended, others=RESERVED.
+ UINT8 DramRonVal; ///< 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control.
+ UINT8 DramRttNomVal; ///< 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED.
+ UINT8 DramRttWrVal; ///< 0=off others=RESERVED.
+ UINT8 SocRdOdtVal; ///< 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED.
+ UINT8 SocWrRonVal; ///< 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED.
+ UINT8 SocWrSlewRate; ///< 0=2.5V/ns, 1=4V/ns, others=RESERVED.
+ UINT8 DramDensity; ///< 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED.
+ UINT32 tRAS; ///< ACT to PRE command period in picoseconds.
+ UINT32 tWTR; ///< Delay from start of internal write transaction to internal read command in picoseconds.
+ UINT32 tRRD; ///< ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds.
+ UINT32 tFAW; ///< Four activate window (JESD79 specific to page size 1K/2K) in picoseconds.
+ UINT8 tCL; ///< DRAM CAS Latency in clocks.
+} PDAT_MRC_ITEM;
+
+//
+// Memory range types
+//
+typedef enum {
+ DualChannelDdrMainMemory,
+ DualChannelDdrSmramCacheable,
+ DualChannelDdrSmramNonCacheable,
+ DualChannelDdrGraphicsMemoryCacheable,
+ DualChannelDdrGraphicsMemoryNonCacheable,
+ DualChannelDdrReservedMemory,
+ DualChannelDdrMaxMemoryRangeType
+} PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE;
+
+//
+// Memory map range information
+//
+typedef struct {
+ EFI_PHYSICAL_ADDRESS PhysicalAddress;
+ EFI_PHYSICAL_ADDRESS CpuAddress;
+ EFI_PHYSICAL_ADDRESS RangeLength;
+ PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE Type;
+} PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE;
+
+//
+// Function prototypes.
+//
+
+EFI_STATUS
+InstallEfiMemory (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,
+ IN EFI_BOOT_MODE BootMode,
+ IN UINT32 TotalMemorySize
+ );
+
+EFI_STATUS
+InstallS3Memory (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,
+ IN UINT32 TotalMemorySize
+ );
+
+EFI_STATUS
+MemoryInit (
+ IN EFI_PEI_SERVICES **PeiServices
+ );
+
+
+EFI_STATUS
+LoadConfig (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,
+ IN OUT MRCParams_t *MrcData
+ );
+
+EFI_STATUS
+SaveConfig (
+ IN MRCParams_t *MrcData
+ );
+
+VOID
+RetriveRequiredMemorySize (
+ IN EFI_PEI_SERVICES **PeiServices,
+ OUT UINTN *Size
+ );
+
+EFI_STATUS
+GetMemoryMap (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN UINT32 TotalMemorySize,
+ IN OUT PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *MemoryMap,
+ IN OUT UINT8 *NumRanges
+ );
+
+EFI_STATUS
+ChooseRanges (
+ IN OUT PEI_MEMORY_RANGE_OPTION_ROM *OptionRomMask,
+ IN OUT PEI_MEMORY_RANGE_SMRAM *SmramMask,
+ IN OUT PEI_MEMORY_RANGE_PCI_MEMORY *PciMemoryMask
+ );
+
+EFI_STATUS
+GetPlatformMemorySize (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_BOOT_MODE BootMode,
+ IN OUT UINT64 *MemorySize
+ );
+
+EFI_STATUS
+BaseMemoryTest (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PHYSICAL_ADDRESS BeginAddress,
+ IN UINT64 MemoryLength,
+ IN PEI_MEMORY_TEST_OP Operation,
+ OUT EFI_PHYSICAL_ADDRESS *ErrorAddress
+ );
+
+EFI_STATUS
+SetPlatformImrPolicy (
+ IN EFI_PHYSICAL_ADDRESS PeiMemoryBaseAddress,
+ IN UINT64 PeiMemoryLength,
+ IN UINTN RequiredMemSize
+ );
+
+VOID
+EFIAPI
+InfoPostInstallMemory (
+ OUT UINT32 *RmuBaseAddressPtr OPTIONAL,
+ OUT EFI_SMRAM_DESCRIPTOR **SmramDescriptorPtr OPTIONAL,
+ OUT UINTN *NumSmramRegionsPtr OPTIONAL
+ );
+
+#endif
diff --git a/QuarkPlatformPkg/Platform/Pei/PlatformInit/PeiFvSecurity.c b/QuarkPlatformPkg/Platform/Pei/PlatformInit/PeiFvSecurity.c new file mode 100644 index 0000000000..d0246be2e0 --- /dev/null +++ b/QuarkPlatformPkg/Platform/Pei/PlatformInit/PeiFvSecurity.c @@ -0,0 +1,117 @@ +/** @file
+EFI PEI Platform Security services
+
+Copyright (c) 2013 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PeiFvSecurity.h"
+
+EFI_PEI_NOTIFY_DESCRIPTOR mNotifyOnFvInfoSecurityList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiFirmwareVolumeInfoPpiGuid,
+ FirmwareVolmeInfoPpiNotifySecurityCallback
+};
+
+/**
+ Callback function to perform FV security checking on a FV Info PPI.
+
+ @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation
+ @param NotifyDescriptor Address of the notification descriptor data structure.
+ @param Ppi Address of the PPI that was installed.
+
+ @retval EFI_SUCCESS
+
+**/
+EFI_STATUS
+EFIAPI
+FirmwareVolmeInfoPpiNotifySecurityCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_FIRMWARE_VOLUME_INFO_PPI *FvInfoPpi;
+ EFI_PEI_FIRMWARE_VOLUME_PPI *FvPpi;
+
+ FvInfoPpi = (EFI_PEI_FIRMWARE_VOLUME_INFO_PPI *)Ppi;
+
+ //
+ // Locate the corresponding FV_PPI according to founded FV's format guid
+ //
+ Status = PeiServicesLocatePpi (
+ &FvInfoPpi->FvFormat,
+ 0,
+ NULL,
+ (VOID**)&FvPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Only authenticate parent Firmware Volume (child firmware volumes are covered by the parent)
+ //
+ if ((VOID *)FvInfoPpi->ParentFvName == NULL && (VOID *)FvInfoPpi->ParentFileName == NULL) {
+ Status = PeiSecurityVerifyFv ((EFI_FIRMWARE_VOLUME_HEADER*) FvInfoPpi->FvInfo);
+ ASSERT_EFI_ERROR (Status);
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Authenticates the Firmware Volume
+
+ @param CurrentFvAddress Pointer to the current Firmware Volume under consideration
+
+ @retval EFI_SUCCESS Firmware Volume is legal
+
+**/
+EFI_STATUS
+PeiSecurityVerifyFv (
+ IN EFI_FIRMWARE_VOLUME_HEADER *CurrentFvAddress
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Call Security library to authenticate the Firmware Volume
+ //
+ DEBUG ((DEBUG_INFO, "PeiSecurityVerifyFv - CurrentFvAddress=0x%8x\n", (UINT32)CurrentFvAddress));
+ Status = EFI_SUCCESS;
+
+ return Status;
+}
+
+/**
+
+ Entry point for the PEI Security PEIM
+ Sets up a notification to perform PEI security checking
+
+ @param FfsHeader Not used.
+ @param PeiServices General purpose services available to every PEIM.
+
+ @return EFI_SUCCESS PEI Security notification installed successfully.
+ All others: PEI Security notification failed to install.
+
+**/
+EFI_STATUS
+PeiInitializeFvSecurity (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ Status = PeiServicesNotifyPpi (&mNotifyOnFvInfoSecurityList);
+
+ return Status;
+}
+
diff --git a/QuarkPlatformPkg/Platform/Pei/PlatformInit/PeiFvSecurity.h b/QuarkPlatformPkg/Platform/Pei/PlatformInit/PeiFvSecurity.h new file mode 100644 index 0000000000..f55b6b8856 --- /dev/null +++ b/QuarkPlatformPkg/Platform/Pei/PlatformInit/PeiFvSecurity.h @@ -0,0 +1,73 @@ +/** @file
+Definition of Pei Core Structures and Services
+
+Copyright (c) 2013 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_FV_SECURITY_H_
+#define _PEI_FV_SECURITY_H_
+
+#include <Ppi/FirmwareVolume.h>
+#include <Ppi/FirmwareVolumeInfo.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+/**
+ Callback function to perform FV security checking on a FV Info PPI.
+
+ @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation
+ @param NotifyDescriptor Address of the notification descriptor data structure.
+ @param Ppi Address of the PPI that was installed.
+
+ @retval EFI_SUCCESS
+
+**/
+EFI_STATUS
+EFIAPI
+FirmwareVolmeInfoPpiNotifySecurityCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+/**
+ Authenticates the Firmware Volume
+
+ @param CurrentFvAddress Pointer to the current Firmware Volume under consideration
+
+ @retval EFI_SUCCESS Firmware Volume is legal
+
+**/
+EFI_STATUS
+PeiSecurityVerifyFv (
+ IN EFI_FIRMWARE_VOLUME_HEADER *CurrentFvAddress
+ );
+
+/**
+
+ Entry point for the PEI Security PEIM
+ Sets up a notification to perform PEI security checking
+
+ @param FfsHeader Not used.
+ @param PeiServices General purpose services available to every PEIM.
+
+ @return EFI_SUCCESS PEI Security notification installed successfully.
+ All others: PEI Security notification failed to install.
+
+**/
+EFI_STATUS
+PeiInitializeFvSecurity (
+ VOID
+ );
+
+#endif
diff --git a/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.c b/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.c new file mode 100644 index 0000000000..32ae3e0891 --- /dev/null +++ b/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.c @@ -0,0 +1,962 @@ +/** @file
+This PEIM initialize platform for MRC, following action is performed,
+1. Initizluize GMCH
+2. Detect boot mode
+3. Detect video adapter to determine whether we need pre allocated memory
+4. Calls MRC to initialize memory and install a PPI notify to do post memory initialization.
+This file contains the main entrypoint of the PEIM.
+
+Copyright (c) 2013 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#include "CommonHeader.h"
+#include "PlatformEarlyInit.h"
+#include "PeiFvSecurity.h"
+
+EFI_STATUS
+EFIAPI
+EndOfPeiSignalPpiNotifyCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+//
+// Function prototypes to routines implemented in other source modules
+// within this component.
+//
+
+EFI_STATUS
+EFIAPI
+PlatformErratasPostMrc (
+ VOID
+ );
+
+//
+// The global indicator, the FvFileLoader callback will modify it to TRUE after loading PEIM into memory
+//
+BOOLEAN ImageInMemory = FALSE;
+
+BOARD_LEGACY_GPIO_CONFIG mBoardLegacyGpioConfigTable[] = { PLATFORM_LEGACY_GPIO_TABLE_DEFINITION };
+UINTN mBoardLegacyGpioConfigTableLen = (sizeof(mBoardLegacyGpioConfigTable) / sizeof(BOARD_LEGACY_GPIO_CONFIG));
+BOARD_GPIO_CONTROLLER_CONFIG mBoardGpioControllerConfigTable[] = { PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION };
+UINTN mBoardGpioControllerConfigTableLen = (sizeof(mBoardGpioControllerConfigTable) / sizeof(BOARD_GPIO_CONTROLLER_CONFIG));
+UINT8 ChipsetDefaultMac [6] = {0xff,0xff,0xff,0xff,0xff,0xff};
+
+EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[1] = {
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiMasterBootModePpiGuid,
+ NULL
+ }
+};
+
+EFI_PEI_NOTIFY_DESCRIPTOR mMemoryDiscoveredNotifyList[1] = {
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiMemoryDiscoveredPpiGuid,
+ MemoryDiscoveredPpiNotifyCallback
+ }
+};
+
+EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiSignalPpiNotifyList[1] = {
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiEndOfPeiSignalPpiGuid,
+ EndOfPeiSignalPpiNotifyCallback
+ }
+};
+
+EFI_PEI_STALL_PPI mStallPpi = {
+ PEI_STALL_RESOLUTION,
+ Stall
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPpiStall[1] = {
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiStallPpiGuid,
+ &mStallPpi
+ }
+};
+
+/**
+ Set Mac address on chipset ethernet device.
+
+ @param Bus PCI Bus number of chipset ethernet device.
+ @param Device Device number of chipset ethernet device.
+ @param Func PCI Function number of chipset ethernet device.
+ @param MacAddr MAC Address to set.
+
+**/
+VOID
+EFIAPI
+SetLanControllerMacAddr (
+ IN CONST UINT8 Bus,
+ IN CONST UINT8 Device,
+ IN CONST UINT8 Func,
+ IN CONST UINT8 *MacAddr,
+ IN CONST UINT32 Bar0
+ )
+{
+ UINT32 Data32;
+ UINT16 PciVid;
+ UINT16 PciDid;
+ UINT32 Addr;
+ UINT32 MacVer;
+ volatile UINT8 *Wrote;
+ UINT32 DevPcieAddr;
+ UINT16 SaveCmdReg;
+ UINT32 SaveBarReg;
+
+ DevPcieAddr = PCI_LIB_ADDRESS (
+ Bus,
+ Device,
+ Func,
+ 0
+ );
+
+ //
+ // Do nothing if not a supported device.
+ //
+ PciVid = PciRead16 (DevPcieAddr + PCI_VENDOR_ID_OFFSET);
+ PciDid = PciRead16 (DevPcieAddr + PCI_DEVICE_ID_OFFSET);
+ if((PciVid != V_IOH_MAC_VENDOR_ID) || (PciDid != V_IOH_MAC_DEVICE_ID)) {
+ return;
+ }
+
+ //
+ // Save current settings for PCI CMD/BAR registers
+ //
+ SaveCmdReg = PciRead16 (DevPcieAddr + PCI_COMMAND_OFFSET);
+ SaveBarReg = PciRead32 (DevPcieAddr + R_IOH_MAC_MEMBAR);
+
+ //
+ // Use predefined tempory memory resource
+ //
+ PciWrite32 ( DevPcieAddr + R_IOH_MAC_MEMBAR, Bar0);
+ PciWrite8 ( DevPcieAddr + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
+
+ Addr = Bar0 + R_IOH_MAC_GMAC_REG_8;
+ MacVer = *((volatile UINT32 *) (UINTN)(Addr));
+
+ DEBUG ((EFI_D_INFO, "Ioh MAC [B:%d, D:%d, F:%d] VER:%04x ADDR:",
+ (UINTN) Bus,
+ (UINTN) Device,
+ (UINTN) Func,
+ (UINTN) MacVer
+ ));
+
+ //
+ // Set MAC Address0 Low Register (GMAC_REG_17) ADDRLO bits.
+ //
+ Addr = Bar0 + R_IOH_MAC_GMAC_REG_17;
+ Data32 = *((UINT32 *) (UINTN)(&MacAddr[0]));
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+ Wrote = (volatile UINT8 *) (UINTN)(Addr);
+ DEBUG ((EFI_D_INFO, "%02x-%02x-%02x-%02x-",
+ (UINTN) Wrote[0],
+ (UINTN) Wrote[1],
+ (UINTN) Wrote[2],
+ (UINTN) Wrote[3]
+ ));
+
+ //
+ // Set MAC Address0 High Register (GMAC_REG_16) ADDRHI bits
+ // and Address Enable (AE) bit.
+ //
+ Addr = Bar0 + R_IOH_MAC_GMAC_REG_16;
+ Data32 =
+ ((UINT32) MacAddr[4]) |
+ (((UINT32)MacAddr[5]) << 8) |
+ B_IOH_MAC_AE;
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+ Wrote = (volatile UINT8 *) (UINTN)(Addr);
+
+ DEBUG ((EFI_D_INFO, "%02x-%02x\n", (UINTN) Wrote[0], (UINTN) Wrote[1]));
+
+ //
+ // Restore settings for PCI CMD/BAR registers
+ //
+ PciWrite32 ((DevPcieAddr + R_IOH_MAC_MEMBAR), SaveBarReg);
+ PciWrite16 (DevPcieAddr + PCI_COMMAND_OFFSET, SaveCmdReg);
+}
+
+/**
+ This is the entrypoint of PEIM
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS if it completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+PeiInitPlatform (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
+ EFI_PEI_STALL_PPI *StallPpi;
+ EFI_PEI_PPI_DESCRIPTOR *StallPeiPpiDescriptor;
+ EFI_FV_FILE_INFO FileInfo;
+ EFI_PLATFORM_TYPE PlatformType;
+
+ PlatformType = (EFI_PLATFORM_TYPE)PcdGet16 (PcdPlatformType);
+
+ //
+ // Initialize Firmware Volume security.
+ // This must be done before any firmware volume accesses (excl. BFV)
+ //
+ Status = PeiInitializeFvSecurity();
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Do any early platform specific initialization.
+ //
+ EarlyPlatformInit ();
+
+ //
+ // This is a second path on entry, in recovery boot path the Stall PPI need to be memory-based
+ // to improve recovery performance.
+ //
+ Status = PeiServicesFfsGetFileInfo (FileHandle, &FileInfo);
+ ASSERT_EFI_ERROR (Status);
+ //
+ // The follow conditional check only works for memory-mapped FFS,
+ // so we ASSERT that the file is really a MM FFS.
+ //
+ ASSERT (FileInfo.Buffer != NULL);
+ if (!(((UINTN) FileInfo.Buffer <= (UINTN) PeiInitPlatform) &&
+ ((UINTN) PeiInitPlatform <= (UINTN) FileInfo.Buffer + FileInfo.BufferSize))) {
+ //
+ // Now that module in memory, update the
+ // PPI that describes the Stall to other modules
+ //
+ Status = PeiServicesLocatePpi (
+ &gEfiPeiStallPpiGuid,
+ 0,
+ &StallPeiPpiDescriptor,
+ (VOID **) &StallPpi
+ );
+
+ if (!EFI_ERROR (Status)) {
+
+ Status = PeiServicesReInstallPpi (
+ StallPeiPpiDescriptor,
+ &mPpiStall[0]
+ );
+ } else {
+
+ Status = PeiServicesInstallPpi (&mPpiStall[0]);
+ }
+ return Status;
+ }
+
+ //
+ // Initialize System Phys
+ //
+
+ // Program USB Phy
+ InitializeUSBPhy();
+
+ //
+ // Do platform specific logic to create a boot mode
+ //
+ Status = UpdateBootMode ((EFI_PEI_SERVICES**)PeiServices, &BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Signal possible dependent modules that there has been a
+ // final boot mode determination
+ //
+ if (!EFI_ERROR(Status)) {
+ Status = PeiServicesInstallPpi (&mPpiBootMode[0]);
+ ASSERT_EFI_ERROR (Status);
+ }
+
+ if (BootMode != BOOT_ON_S3_RESUME) {
+ QNCClearSmiAndWake ();
+ }
+
+ DEBUG ((EFI_D_INFO, "MRC Entry\n"));
+ MemoryInit ((EFI_PEI_SERVICES**)PeiServices);
+
+ //
+ // Do Early PCIe init.
+ //
+ DEBUG ((EFI_D_INFO, "Early PCIe controller initialization\n"));
+ PlatformPciExpressEarlyInit (PlatformType);
+
+
+ DEBUG ((EFI_D_INFO, "Platform Erratas After MRC\n"));
+ PlatformErratasPostMrc ();
+
+ //
+ // Now that all of the pre-permanent memory activities have
+ // been taken care of, post a call-back for the permanent-memory
+ // resident services, such as HOB construction.
+ // PEI Core will switch stack after this PEIM exit. After that the MTRR
+ // can be set.
+ //
+ Status = PeiServicesNotifyPpi (&mMemoryDiscoveredNotifyList[0]);
+ ASSERT_EFI_ERROR (Status);
+/*
+
+ if (BootMode != BOOT_ON_S3_RESUME) {
+ Status = PeiServicesNotifyPpi (mEndOfPeiSignalPpiNotifyList);
+ ASSERT_EFI_ERROR (Status);
+ }
+*/
+ if (BootMode == BOOT_IN_RECOVERY_MODE) {
+ PeiServicesRegisterForShadow (FileHandle);
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+EFIAPI
+EndOfPeiSignalPpiNotifyCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((EFI_D_INFO, "End of PEI Signal Callback\n"));
+
+ //
+ // Restore the flash region to be UC
+ // for both normal boot as we build a Resource Hob to
+ // describe this region as UC to DXE core.
+ //
+ WriteBackInvalidateDataCacheRange (
+ (VOID *) (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),
+ PcdGet32 (PcdFlashAreaSize)
+ );
+
+ Status = MtrrSetMemoryAttribute (PcdGet32 (PcdFlashAreaBaseAddress), PcdGet32 (PcdFlashAreaSize), CacheUncacheable);
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function will initialize USB Phy registers associated with QuarkSouthCluster.
+
+ @param VOID No Argument
+
+ @retval EFI_SUCCESS All registers have been initialized
+**/
+VOID
+EFIAPI
+InitializeUSBPhy (
+ VOID
+ )
+{
+ UINT32 RegData32;
+
+ /** In order to configure the PHY to use clk120 (ickusbcoreclk) as PLL reference clock
+ * and Port2 as a USB device port, the following sequence must be followed
+ *
+ **/
+
+ // Sideband register write to USB AFE (Phy)
+ RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_GLOBAL_PORT);
+ RegData32 &= ~(BIT1);
+ //
+ // Sighting #4930631 PDNRESCFG [8:7] of USB2_GLOBAL_PORT = 11b.
+ // For port 0 & 1 as host and port 2 as device.
+ //
+ RegData32 |= (BIT8 | BIT7);
+ QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_GLOBAL_PORT, RegData32);
+
+ //
+ // Sighting #4930653 Required BIOS change on Disconnect vref to change to 600mV.
+ //
+ RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_COMPBG);
+ RegData32 &= ~(BIT10 | BIT9 | BIT8 | BIT7);
+ RegData32 |= (BIT10 | BIT7);
+ QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_COMPBG, RegData32);
+
+ // Sideband register write to USB AFE (Phy)
+ // (pllbypass) to bypass/Disable PLL before switch
+ RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2);
+ RegData32 |= BIT29;
+ QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2, RegData32);
+
+ // Sideband register write to USB AFE (Phy)
+ // (coreclksel) to select 120MHz (ickusbcoreclk) clk source.
+ // (Default 0 to select 96MHz (ickusbclk96_npad/ppad))
+ RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL1);
+ RegData32 |= BIT1;
+ QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL1, RegData32);
+
+ // Sideband register write to USB AFE (Phy)
+ // (divide by 8) to achieve internal 480MHz clock
+ // for 120MHz input refclk. (Default: 4'b1000 (divide by 10) for 96MHz)
+ RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL1);
+ RegData32 &= ~(BIT5 | BIT4 | BIT3);
+ RegData32 |= BIT6;
+ QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL1, RegData32);
+
+ // Sideband register write to USB AFE (Phy)
+ // Clear (pllbypass)
+ RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2);
+ RegData32 &= ~BIT29;
+ QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2, RegData32);
+
+ // Sideband register write to USB AFE (Phy)
+ // Set (startlock) to force the PLL FSM to restart the lock
+ // sequence due to input clock/freq switch.
+ RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2);
+ RegData32 |= BIT24;
+ QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2, RegData32);
+
+ // At this point the PLL FSM and COMP FSM will complete
+
+}
+
+/**
+ This function provides early platform Thermal sensor initialisation.
+**/
+VOID
+EFIAPI
+EarlyPlatformThermalSensorInit (
+ VOID
+ )
+{
+ DEBUG ((EFI_D_INFO, "Early Platform Thermal Sensor Init\n"));
+
+ //
+ // Set Thermal sensor mode.
+ //
+ QNCThermalSensorSetRatiometricMode ();
+
+ //
+ // Enable RMU Thermal sensor with a Catastrophic Trip point.
+ //
+ QNCThermalSensorEnableWithCatastrophicTrip (PLATFORM_CATASTROPHIC_TRIP_CELSIUS);
+
+ //
+ // Lock all RMU Thermal sensor control & trip point registers.
+ //
+ QNCThermalSensorLockAllRegisters ();
+}
+
+/**
+ Print early platform info messages includeing the Stage1 module that's
+ running, MFH item list and platform data item list.
+**/
+VOID
+EFIAPI
+EarlyPlatformInfoMessages (
+ VOID
+ )
+{
+ DEBUG_CODE_BEGIN ();
+ QUARK_EDKII_STAGE1_HEADER *Edk2ImageHeader;
+
+ //
+ // Find which 'Stage1' image we are running and print the details
+ //
+ Edk2ImageHeader = (QUARK_EDKII_STAGE1_HEADER *) PcdGet32 (PcdEsramStage1Base);
+ DEBUG ((EFI_D_INFO, "\n************************************************************\n"));
+
+ switch ((UINT8)Edk2ImageHeader->ImageIndex & QUARK_STAGE1_IMAGE_TYPE_MASK) {
+ case QUARK_STAGE1_BOOT_IMAGE_TYPE:
+ DEBUG ((EFI_D_INFO, "**** Quark EDKII Stage 1 Boot Image %d ****\n", ((UINT8)Edk2ImageHeader->ImageIndex & ~(QUARK_STAGE1_IMAGE_TYPE_MASK))));
+ break;
+
+ case QUARK_STAGE1_RECOVERY_IMAGE_TYPE:
+ DEBUG ((EFI_D_INFO, "**** Quark EDKII Stage 1 Recovery Image %d ****\n", ((UINT8)Edk2ImageHeader->ImageIndex & ~(QUARK_STAGE1_IMAGE_TYPE_MASK))));
+ break;
+
+ default:
+ DEBUG ((EFI_D_INFO, "**** Quark EDKII Unknown Stage 1 Image !!!! ****\n"));
+ break;
+ }
+ DEBUG (
+ (EFI_D_INFO,
+ "**** Quark EDKII Stage 2 Image 0x%08X:0x%08X ****\n" ,
+ (UINTN) PcdGet32 (PcdFlashFvMainBase),
+ (UINTN) PcdGet32 (PcdFlashFvMainSize)
+ ));
+
+ DEBUG (
+ (EFI_D_INFO,
+ "**** Quark EDKII Payload Image 0x%08X:0x%08X ****\n" ,
+ (UINTN) PcdGet32 (PcdFlashFvPayloadBase),
+ (UINTN) PcdGet32 (PcdFlashFvPayloadSize)
+ ));
+
+ DEBUG ((EFI_D_INFO, "************************************************************\n\n"));
+
+ DEBUG_CODE_END ();
+}
+
+/**
+ Check if system reset due to error condition.
+
+ @param ClearErrorBits If TRUE clear error flags and value bits.
+
+ @retval TRUE if system reset due to error condition.
+ @retval FALSE if NO reset error conditions.
+**/
+BOOLEAN
+CheckForResetDueToErrors (
+ IN BOOLEAN ClearErrorBits
+ )
+{
+ UINT32 RegValue;
+ BOOLEAN ResetDueToError;
+
+ ResetDueToError = FALSE;
+
+ //
+ // Check if RMU reset system due to access violations.
+ // RMU updates a SOC Unit register before reseting the system.
+ //
+ RegValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW);
+ if ((RegValue & B_CFG_STICKY_RW_VIOLATION) != 0) {
+ ResetDueToError = TRUE;
+
+ DEBUG (
+ (EFI_D_ERROR,
+ "\nReset due to access violation: %s %s %s %s\n",
+ ((RegValue & B_CFG_STICKY_RW_IMR_VIOLATION) != 0) ? L"'IMR'" : L".",
+ ((RegValue & B_CFG_STICKY_RW_DECC_VIOLATION) != 0) ? L"'DECC'" : L".",
+ ((RegValue & B_CFG_STICKY_RW_SMM_VIOLATION) != 0) ? L"'SMM'" : L".",
+ ((RegValue & B_CFG_STICKY_RW_HMB_VIOLATION) != 0) ? L"'HMB'" : L"."
+ ));
+
+ //
+ // Clear error bits.
+ //
+ if (ClearErrorBits) {
+ RegValue &= ~(B_CFG_STICKY_RW_VIOLATION);
+ QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW, RegValue);
+ }
+ }
+
+ return ResetDueToError;
+}
+
+/**
+ This function provides early platform initialization.
+
+ @param PlatformInfo Pointer to platform Info structure.
+
+**/
+VOID
+EFIAPI
+EarlyPlatformInit (
+ VOID
+ )
+{
+ EFI_PLATFORM_TYPE PlatformType;
+
+ PlatformType = (EFI_PLATFORM_TYPE) PcdGet16 (PcdPlatformType);
+
+ DEBUG ((EFI_D_INFO, "EarlyPlatformInit for PlatType=0x%02x\n", (UINTN) PlatformType));
+
+ //
+ // Check if system reset due to error condition.
+ //
+ if (CheckForResetDueToErrors (TRUE)) {
+ if(FeaturePcdGet (WaitIfResetDueToError)) {
+ DEBUG ((EFI_D_ERROR, "Press any key to continue.\n"));
+ PlatformDebugPortGetChar8 ();
+ }
+ }
+
+ //
+ // Display platform info messages.
+ //
+ EarlyPlatformInfoMessages ();
+
+ //
+ // Early Legacy Gpio Init.
+ //
+ EarlyPlatformLegacyGpioInit (PlatformType);
+
+ //
+ // Early platform Legacy GPIO manipulation depending on GPIOs
+ // setup by EarlyPlatformLegacyGpioInit.
+ //
+ EarlyPlatformLegacyGpioManipulation (PlatformType);
+
+ //
+ // Early platform specific GPIO Controller init & manipulation.
+ // Combined for sharing of temp. memory bar.
+ //
+ EarlyPlatformGpioCtrlerInitAndManipulation (PlatformType);
+
+ //
+ // Early Thermal Sensor Init.
+ //
+ EarlyPlatformThermalSensorInit ();
+
+ //
+ // Early Lan Ethernet Mac Init.
+ //
+ EarlyPlatformMacInit (
+ PcdGetPtr (PcdIohEthernetMac0),
+ PcdGetPtr (PcdIohEthernetMac1)
+ );
+}
+
+/**
+ This function provides early platform Legacy GPIO initialisation.
+
+ @param PlatformType Platform type for GPIO init.
+
+**/
+VOID
+EFIAPI
+EarlyPlatformLegacyGpioInit (
+ IN CONST EFI_PLATFORM_TYPE PlatformType
+ )
+{
+ BOARD_LEGACY_GPIO_CONFIG *LegacyGpioConfig;
+ UINT32 NewValue;
+ UINT32 GpioBaseAddress;
+
+ //
+ // Assert if platform type outside table range.
+ //
+ ASSERT ((UINTN) PlatformType < mBoardLegacyGpioConfigTableLen);
+ LegacyGpioConfig = &mBoardLegacyGpioConfigTable[(UINTN) PlatformType];
+
+ GpioBaseAddress = (UINT32)PcdGet16 (PcdGbaIoBaseAddress);
+
+ NewValue = 0x0;
+ //
+ // Program QNC GPIO Registers.
+ //
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGEN_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellEnable;
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGEN_CORE_WELL, NewValue );
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGIO_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellIoSelect;
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGIO_CORE_WELL, NewValue);
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGLVL_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellLvlForInputOrOutput;
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGLVL_CORE_WELL, NewValue);
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGTPE_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellTriggerPositiveEdge;
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGTPE_CORE_WELL, NewValue );
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGTNE_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellTriggerNegativeEdge;
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGTNE_CORE_WELL, NewValue);
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGGPE_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellGPEEnable;
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGGPE_CORE_WELL, NewValue);
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGSMI_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellSMIEnable;
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGSMI_CORE_WELL, NewValue );
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGTS_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellTriggerStatus;
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGTS_CORE_WELL, NewValue);
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CNMIEN_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellNMIEnable;
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CNMIEN_CORE_WELL, NewValue);
+
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGEN_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellEnable;
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGEN_RESUME_WELL, NewValue );
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGIO_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellIoSelect;
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGIO_RESUME_WELL, NewValue) ;
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGLVL_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellLvlForInputOrOutput;
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGLVL_RESUME_WELL, NewValue);
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGTPE_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellTriggerPositiveEdge;
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGTPE_RESUME_WELL, NewValue );
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGTNE_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellTriggerNegativeEdge;
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGTNE_RESUME_WELL, NewValue) ;
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGGPE_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellGPEEnable;
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGGPE_RESUME_WELL, NewValue);
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGSMI_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellSMIEnable;
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGSMI_RESUME_WELL, NewValue );
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGTS_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellTriggerStatus;
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGTS_RESUME_WELL, NewValue) ;
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RNMIEN_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellNMIEnable;
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RNMIEN_RESUME_WELL, NewValue);
+}
+
+/**
+ Performs any early platform specific Legacy GPIO manipulation.
+
+ @param PlatformType Platform type GPIO manipulation.
+
+**/
+VOID
+EFIAPI
+EarlyPlatformLegacyGpioManipulation (
+ IN CONST EFI_PLATFORM_TYPE PlatformType
+ )
+{
+ if (PlatformType == CrossHill) {
+
+ //
+ // Pull TPM reset low for 80us (equivalent to cold reset, Table 39
+ // Infineon SLB9645 Databook), then pull TPM reset high and wait for
+ // 150ms to give time for TPM to stabilise (Section 4.7.1 Infineon
+ // SLB9645 Databook states TPM is ready to receive command after 30ms
+ // but section 4.7 states some TPM commands may take longer to execute
+ // upto 150ms after test).
+ //
+
+ PlatformLegacyGpioSetLevel (
+ R_QNC_GPIO_RGLVL_RESUME_WELL,
+ PLATFORM_RESUMEWELL_TPM_RST_GPIO,
+ FALSE
+ );
+ MicroSecondDelay (80);
+
+ PlatformLegacyGpioSetLevel (
+ R_QNC_GPIO_RGLVL_RESUME_WELL,
+ PLATFORM_RESUMEWELL_TPM_RST_GPIO,
+ TRUE
+ );
+ MicroSecondDelay (150000);
+ }
+
+}
+
+/**
+ Performs any early platform specific GPIO Controller init & manipulation.
+
+ @param PlatformType Platform type for GPIO init & manipulation.
+
+**/
+VOID
+EFIAPI
+EarlyPlatformGpioCtrlerInitAndManipulation (
+ IN CONST EFI_PLATFORM_TYPE PlatformType
+ )
+{
+ UINT32 IohGpioBase;
+ UINT32 Data32;
+ UINT32 Addr;
+ BOARD_GPIO_CONTROLLER_CONFIG *GpioConfig;
+ UINT32 DevPcieAddr;
+ UINT16 SaveCmdReg;
+ UINT32 SaveBarReg;
+ UINT16 PciVid;
+ UINT16 PciDid;
+
+ ASSERT ((UINTN) PlatformType < mBoardGpioControllerConfigTableLen);
+ GpioConfig = &mBoardGpioControllerConfigTable[(UINTN) PlatformType];
+
+ IohGpioBase = (UINT32) PcdGet64 (PcdIohGpioMmioBase);
+
+ DevPcieAddr = PCI_LIB_ADDRESS (
+ PcdGet8 (PcdIohGpioBusNumber),
+ PcdGet8 (PcdIohGpioDevNumber),
+ PcdGet8 (PcdIohGpioFunctionNumber),
+ 0
+ );
+
+ //
+ // Do nothing if not a supported device.
+ //
+ PciVid = PciRead16 (DevPcieAddr + PCI_VENDOR_ID_OFFSET);
+ PciDid = PciRead16 (DevPcieAddr + PCI_DEVICE_ID_OFFSET);
+ if((PciVid != V_IOH_I2C_GPIO_VENDOR_ID) || (PciDid != V_IOH_I2C_GPIO_DEVICE_ID)) {
+ return;
+ }
+
+ //
+ // Save current settings for PCI CMD/BAR registers.
+ //
+ SaveCmdReg = PciRead16 (DevPcieAddr + PCI_COMMAND_OFFSET);
+ SaveBarReg = PciRead32 (DevPcieAddr + PcdGet8 (PcdIohGpioBarRegister));
+
+ //
+ // Use predefined tempory memory resource.
+ //
+ PciWrite32 ( DevPcieAddr + PcdGet8 (PcdIohGpioBarRegister), IohGpioBase);
+ PciWrite8 ( DevPcieAddr + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
+
+ //
+ // Gpio Controller Init Tasks.
+ //
+
+ //
+ // IEN- Interrupt Enable Register
+ //
+ Addr = IohGpioBase + GPIO_INTEN;
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
+ Data32 |= (GpioConfig->IntEn & 0x000FFFFF);
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ //
+ // ISTATUS- Interrupt Status Register
+ //
+ Addr = IohGpioBase + GPIO_INTSTATUS;
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ //
+ // GPIO SWPORTA Direction Register - GPIO_SWPORTA_DR
+ //
+ Addr = IohGpioBase + GPIO_SWPORTA_DR;
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
+ Data32 |= (GpioConfig->PortADR & 0x000FFFFF);
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ //
+ // GPIO SWPORTA Data Direction Register - GPIO_SWPORTA_DDR - default input
+ //
+ Addr = IohGpioBase + GPIO_SWPORTA_DDR;
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
+ Data32 |= (GpioConfig->PortADir & 0x000FFFFF);
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ //
+ // Interrupt Mask Register - GPIO_INTMASK - default interrupts unmasked
+ //
+ Addr = IohGpioBase + GPIO_INTMASK;
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
+ Data32 |= (GpioConfig->IntMask & 0x000FFFFF);
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ //
+ // Interrupt Level Type Register - GPIO_INTTYPE_LEVEL - default is level sensitive
+ //
+ Addr = IohGpioBase + GPIO_INTTYPE_LEVEL;
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
+ Data32 |= (GpioConfig->IntType & 0x000FFFFF);
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ //
+ // Interrupt Polarity Type Register - GPIO_INT_POLARITY - default is active low
+ //
+ Addr = IohGpioBase + GPIO_INT_POLARITY;
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
+ Data32 |= (GpioConfig->IntPolarity & 0x000FFFFF);
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ //
+ // Interrupt Debounce Type Register - GPIO_DEBOUNCE - default no debounce
+ //
+ Addr = IohGpioBase + GPIO_DEBOUNCE;
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
+ Data32 |= (GpioConfig->Debounce & 0x000FFFFF);
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ //
+ // Interrupt Clock Synchronisation Register - GPIO_LS_SYNC - default no sync with pclk_intr(APB bus clk)
+ //
+ Addr = IohGpioBase + GPIO_LS_SYNC;
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
+ Data32 |= (GpioConfig->LsSync & 0x000FFFFF);
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ //
+ // Gpio Controller Manipulation Tasks.
+ //
+
+ if (PlatformType == (EFI_PLATFORM_TYPE) Galileo) {
+ //
+ // Reset Cypress Expander on Galileo Platform
+ //
+ Addr = IohGpioBase + GPIO_SWPORTA_DR;
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr));
+ Data32 |= BIT4; // Cypress Reset line controlled by GPIO<4>
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr));
+ Data32 &= ~BIT4; // Cypress Reset line controlled by GPIO<4>
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ }
+
+ //
+ // Restore settings for PCI CMD/BAR registers
+ //
+ PciWrite32 ((DevPcieAddr + PcdGet8 (PcdIohGpioBarRegister)), SaveBarReg);
+ PciWrite16 (DevPcieAddr + PCI_COMMAND_OFFSET, SaveCmdReg);
+}
+
+/**
+ Performs any early platform init of SoC Ethernet Mac devices.
+
+ @param IohMac0Address Mac address to program into Mac0 device.
+ @param IohMac1Address Mac address to program into Mac1 device.
+
+**/
+VOID
+EFIAPI
+EarlyPlatformMacInit (
+ IN CONST UINT8 *IohMac0Address,
+ IN CONST UINT8 *IohMac1Address
+ )
+{
+ BOOLEAN SetMacAddr;
+
+ //
+ // Set chipset MAC0 address if configured.
+ //
+ SetMacAddr =
+ (CompareMem (ChipsetDefaultMac, IohMac0Address, sizeof (ChipsetDefaultMac))) != 0;
+ if (SetMacAddr) {
+ if ((*(IohMac0Address) & BIT0) != 0) {
+ DEBUG ((EFI_D_ERROR, "HALT: Multicast Mac Address configured for Ioh MAC [B:%d, D:%d, F:%d]\n",
+ (UINTN) IOH_MAC0_BUS_NUMBER,
+ (UINTN) IOH_MAC0_DEVICE_NUMBER,
+ (UINTN) IOH_MAC0_FUNCTION_NUMBER
+ ));
+ ASSERT (FALSE);
+ } else {
+ SetLanControllerMacAddr (
+ IOH_MAC0_BUS_NUMBER,
+ IOH_MAC0_DEVICE_NUMBER,
+ IOH_MAC0_FUNCTION_NUMBER,
+ IohMac0Address,
+ (UINT32) PcdGet64(PcdIohMac0MmioBase)
+ );
+ }
+ } else {
+ DEBUG ((EFI_D_WARN, "WARNING: Ioh MAC [B:%d, D:%d, F:%d] NO HW ADDR CONFIGURED!!!\n",
+ (UINTN) IOH_MAC0_BUS_NUMBER,
+ (UINTN) IOH_MAC0_DEVICE_NUMBER,
+ (UINTN) IOH_MAC0_FUNCTION_NUMBER
+ ));
+ }
+
+ //
+ // Set chipset MAC1 address if configured.
+ //
+ SetMacAddr =
+ (CompareMem (ChipsetDefaultMac, IohMac1Address, sizeof (ChipsetDefaultMac))) != 0;
+ if (SetMacAddr) {
+ if ((*(IohMac1Address) & BIT0) != 0) {
+ DEBUG ((EFI_D_ERROR, "HALT: Multicast Mac Address configured for Ioh MAC [B:%d, D:%d, F:%d]\n",
+ (UINTN) IOH_MAC1_BUS_NUMBER,
+ (UINTN) IOH_MAC1_DEVICE_NUMBER,
+ (UINTN) IOH_MAC1_FUNCTION_NUMBER
+ ));
+ ASSERT (FALSE);
+ } else {
+ SetLanControllerMacAddr (
+ IOH_MAC1_BUS_NUMBER,
+ IOH_MAC1_DEVICE_NUMBER,
+ IOH_MAC1_FUNCTION_NUMBER,
+ IohMac1Address,
+ (UINT32) PcdGet64(PcdIohMac1MmioBase)
+ );
+ }
+ } else {
+ DEBUG ((EFI_D_WARN, "WARNING: Ioh MAC [B:%d, D:%d, F:%d] NO HW ADDR CONFIGURED!!!\n",
+ (UINTN) IOH_MAC1_BUS_NUMBER,
+ (UINTN) IOH_MAC1_DEVICE_NUMBER,
+ (UINTN) IOH_MAC1_FUNCTION_NUMBER
+ ));
+ }
+}
+
diff --git a/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.h b/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.h new file mode 100644 index 0000000000..02d97e8e94 --- /dev/null +++ b/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.h @@ -0,0 +1,307 @@ +/** @file
+The header file of Platform PEIM.
+
+Copyright (c) 2013 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#ifndef __PLATFORM_EARLY_INIT_H__
+#define __PLATFORM_EARLY_INIT_H__
+
+#define PEI_STALL_RESOLUTION 1
+#define STALL_PEIM_SIGNATURE SIGNATURE_32('p','p','u','s')
+
+typedef struct {
+ UINT32 Signature;
+ EFI_FFS_FILE_HEADER *FfsHeader;
+ EFI_PEI_NOTIFY_DESCRIPTOR StallNotify;
+} STALL_CALLBACK_STATE_INFORMATION;
+
+#define STALL_PEIM_FROM_THIS(a) CR (a, STALL_CALLBACK_STATE_INFORMATION, StallNotify, STALL_PEIM_SIGNATURE)
+
+//
+// USB Phy Registers
+//
+#define USB2_GLOBAL_PORT 0x4001
+#define USB2_PLL1 0x7F02
+#define USB2_PLL2 0x7F03
+#define USB2_COMPBG 0x7F04
+
+/**
+ Peform the boot mode determination logic
+ If the box is closed, then
+ 1. If it's first time to boot, it's boot with full config .
+ 2. If the ChassisIntrution is selected, force to be a boot with full config
+ 3. Otherwise it's boot with no change.
+
+ @param PeiServices General purpose services available to every PEIM.
+
+ @param BootMode The detected boot mode.
+
+ @retval EFI_SUCCESS if the boot mode could be set
+**/
+EFI_STATUS
+UpdateBootMode (
+ IN EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_BOOT_MODE *BootMode
+ );
+
+/**
+ This function reset the entire platform, including all processor and devices, and
+ reboots the system.
+
+ @param PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS if it completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+ResetSystem (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+/**
+ This function will be called when MRC is done.
+
+ @param PeiServices General purpose services available to every PEIM.
+
+ @param NotifyDescriptor Information about the notify event..
+
+ @param Ppi The notify context.
+
+ @retval EFI_SUCCESS If the function completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+MemoryDiscoveredPpiNotifyCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+/**
+ This is the callback function notified by FvFileLoader PPI, it depends on FvFileLoader PPI to load
+ the PEIM into memory.
+
+ @param PeiServices General purpose services available to every PEIM.
+ @param NotifyDescriptor The context of notification.
+ @param Ppi The notify PPI.
+
+ @retval EFI_SUCCESS if it completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+FvFileLoaderPpiNotifyCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+/**
+ This function provides a blocking stall for reset at least the given number of microseconds
+ stipulated in the final argument.
+
+ @param PeiServices General purpose services available to every PEIM.
+
+ @param this Pointer to the local data for the interface.
+
+ @param Microseconds number of microseconds for which to stall.
+
+ @retval EFI_SUCCESS the function provided at least the required stall.
+**/
+EFI_STATUS
+EFIAPI
+Stall (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_STALL_PPI *This,
+ IN UINTN Microseconds
+ );
+
+/**
+ This function initialize recovery functionality by installing the recovery PPI.
+
+ @param PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS if the interface could be successfully installed.
+**/
+EFI_STATUS
+EFIAPI
+PeimInitializeRecovery (
+ IN EFI_PEI_SERVICES **PeiServices
+ );
+
+/**
+ This function
+ 1. Calling MRC to initialize memory.
+ 2. Install EFI Memory.
+ 3. Create HOB of system memory.
+
+ @param PeiServices Pointer to the PEI Service Table
+
+ @retval EFI_SUCCESS If it completes successfully.
+
+**/
+EFI_STATUS
+MemoryInit (
+ IN EFI_PEI_SERVICES **PeiServices
+ );
+
+/** Return info derived from Installing Memory by MemoryInit.
+
+ @param[out] RmuMainBaseAddressPtr Return RmuMainBaseAddress to this location.
+ @param[out] SmramDescriptorPtr Return start of Smram descriptor list to this location.
+ @param[out] NumSmramRegionsPtr Return numbers of Smram regions to this location.
+
+ @return Address of RMU shadow region at the top of available memory.
+ @return List of Smram descriptors for each Smram region.
+ @return Numbers of Smram regions.
+**/
+VOID
+EFIAPI
+InfoPostInstallMemory (
+ OUT UINT32 *RmuMainBaseAddressPtr OPTIONAL,
+ OUT EFI_SMRAM_DESCRIPTOR **SmramDescriptorPtr OPTIONAL,
+ OUT UINTN *NumSmramRegionsPtr OPTIONAL
+ );
+
+/**
+ This function provides the implementation of AtaController PPI Enable Channel function.
+
+ @param PeiServices General purpose services available to every PEIM.
+ @param this Pointer to the local data for the interface.
+ @param ChannelMask This parameter is used to specify primary or slavery IDE channel.
+
+ @retval EFI_SUCCESS Procedure returned successfully.
+**/
+
+EFI_STATUS
+EnableAtaChannel (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_ATA_CONTROLLER_PPI *This,
+ IN UINT8 ChannelMask
+ );
+
+/**
+ This function provides the implementation of AtaController PPI Get IDE channel Register Base Address
+
+ @param PeiServices General purpose services available to every PEIM.
+ @param this Pointer to the local data for the interface.
+ @param IdeRegsBaseAddr Pointer to IDE_REGS_BASE_ADDR struct, which is used to record
+ IDE Command and Control regeisters Base Address.
+
+ @retval EFI_SUCCESS Procedure returned successfully.
+**/
+
+EFI_STATUS
+GetIdeRegsBaseAddr (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_ATA_CONTROLLER_PPI *This,
+ IN IDE_REGS_BASE_ADDR *IdeRegsBaseAddr
+ );
+
+VOID
+EFIAPI
+InitializeUSBPhy (
+ VOID
+ );
+
+/**
+ This function provides early platform initialisation.
+
+ @param PlatformInfo Pointer to platform Info structure.
+
+**/
+VOID
+EFIAPI
+EarlyPlatformInit (
+ VOID
+ );
+
+/**
+ This function provides early platform GPIO initialisation.
+
+ @param PlatformType Platform type for GPIO init.
+
+**/
+VOID
+EFIAPI
+EarlyPlatformLegacyGpioInit (
+ IN CONST EFI_PLATFORM_TYPE PlatformType
+ );
+
+/**
+ Performs any early platform specific GPIO manipulation.
+
+ @param PlatformType Platform type GPIO manipulation.
+
+**/
+VOID
+EFIAPI
+EarlyPlatformLegacyGpioManipulation (
+ IN CONST EFI_PLATFORM_TYPE PlatformType
+ );
+
+/**
+ Performs any early platform specific GPIO Controller init & manipulation.
+
+ @param PlatformType Platform type for GPIO init & manipulation.
+
+**/
+VOID
+EFIAPI
+EarlyPlatformGpioCtrlerInitAndManipulation (
+ IN CONST EFI_PLATFORM_TYPE PlatformType
+ );
+
+/**
+ Performs any early platform init of SoC Ethernet Mac devices.
+
+ @param IohMac0Address Mac address to program into Mac0 device.
+ @param IohMac1Address Mac address to program into Mac1 device.
+
+**/
+VOID
+EFIAPI
+EarlyPlatformMacInit (
+ IN CONST UINT8 *IohMac0Address,
+ IN CONST UINT8 *IohMac1Address
+ );
+
+/**
+ Find security headers using EFI_CAPSULE_VARIABLE_NAME variables and build Hobs.
+
+ @param PeiServices General purpose services available to every PEIM.
+
+ @retval 0 if no security headers found.
+ @return number of security header hobs built.
+**/
+UINTN
+EFIAPI
+FindCapsuleSecurityHeadersAndBuildHobs (
+ IN EFI_PEI_SERVICES **PeiServices
+ );
+
+/**
+ Build capsule security header hob.
+
+ @param SecHdr Pointer to security header.
+
+ @retval NULL if failure to build HOB.
+ @return pointer to built hob.
+**/
+VOID *
+EFIAPI
+BuildCapsuleSecurityHeaderHob (
+ IN VOID *SecHdr
+ );
+
+#endif
diff --git a/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf b/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf new file mode 100644 index 0000000000..dd373defdb --- /dev/null +++ b/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf @@ -0,0 +1,200 @@ +## @file
+# This is the Platform PEIM to initialize whole platform on PEI phase.
+#
+# This PEIM includes 3 parts, pre memory initialization, MRC
+# wrapper and post memory initialization.
+# On pre memory, following action is performed,
+# 1. Initizluize GMCH.
+# 2. Detect boot mode.
+# 3. Detect video adapter to determine whether we need pre allocated
+# memory.
+#
+# After that MRC wrapper calls MRC to initialize memory and install a PPI
+# notify to do post memory
+# initialization. MRC wrapper performance following actions,
+# 1. Install EFI Memory.
+# 2. Create HOB of system memory.
+#
+# On post memory, following action is performed,
+# 1. QNC initialization after MRC.
+# 2. SIO initialization.
+# 3. Install ResetSystem and FinvFv PPI, relocate Stall to memory on
+# recovery boot mode.
+# 4. Set MTRR for PEI
+# 5. Create FV HOB and Flash HOB
+# 6. Install RecoveryModule and AtaController PPI if on recovery boot mode.
+#
+# This PEIM does not have any register access directly, it depends on
+# IntelQNCLib, QNCAccess libraries to access Chipset
+# registers.
+#
+# Platform.c - Provide main flow and entrypoint of PEIM.
+# MemoryCallback.c - Includes a memory call back function notified when
+# MRC is done.
+# Recovery.c - provides the platform recoveyr functionality.
+# MrcWrapper.c - Contains the logic to call MRC PPI and do Framework
+# memory specific stuff like build memory map, build
+# resource description hob for DXE phase,etc.
+# Bootmode.c - Detect boot mode.
+# Copyright (c) 2013 Intel Corporation.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformEarlyInitPei
+ FILE_GUID = 9618C0DC-50A4-496c-994F-7241F282ED01
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PeiInitPlatform
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources]
+ Generic/Recovery.c
+ PlatformErratas.c
+ MrcWrapper.c
+ MrcWrapper.h
+ PlatformEarlyInit.c
+ PlatformEarlyInit.h
+ MemoryCallback.c
+ BootMode.c
+ CommonHeader.h
+ PeiFvSecurity.c
+ PeiFvSecurity.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelFrameworkPkg/IntelFrameworkPkg.dec
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
+ QuarkPlatformPkg/QuarkPlatformPkg.dec
+ QuarkSocPkg/QuarkSocPkg.dec
+
+[LibraryClasses]
+ ResetSystemLib
+ PrintLib
+ TimerLib
+ RecoveryOemHookLib
+ PcdLib
+ IntelQNCLib
+ ReportStatusCodeLib
+ PciLib
+ PciExpressLib
+ IoLib
+ PciCf8Lib
+ HobLib
+ BaseMemoryLib
+ PeiServicesTablePointerLib
+ PeiServicesLib
+ BaseLib
+ PeimEntryPoint
+ DebugLib
+ MemoryAllocationLib
+ PerformanceLib
+ CacheMaintenanceLib
+ MtrrLib
+ QNCAccessLib
+ PlatformHelperLib
+ PlatformPcieHelperLib
+
+[Guids]
+ gEfiMemoryConfigDataGuid # ALWAYS_CONSUMED L"MemoryConfig"
+ gEfiAcpiVariableGuid # ALWAYS_CONSUMED L"AcpiGlobalVariab"
+ gEfiMemoryTypeInformationGuid # ALWAYS_CONSUMED L"MemoryTypeInformation"
+ gEfiMemoryConfigDataGuid # SOMETIMES_PRODUCED Hob: GUID_EXTENSION
+ gEfiSmmPeiSmramMemoryReserveGuid # ALWAYS_PRODUCED Hob: GUID_EXTENSION
+ gEfiFirmwareFileSystem2Guid # ALWAYS_CONSUMED
+ gEfiCapsuleGuid # ALWAYS_CONSUMED
+ gPeiCapsuleOnDataCDGuid
+ gPeiCapsuleOnFatIdeDiskGuid
+ gPeiCapsuleOnFatUsbDiskGuid
+ gEfiMemoryOverwriteControlDataGuid # SOMETIMES_CONSUMED
+ gEfiQuarkCapsuleGuid
+
+[Ppis]
+ gQNCMemoryInitPpiGuid # PPI ALWAYS_CONSUMED
+ gEfiPeiMemoryDiscoveredPpiGuid # PPI ALWAYS_PRODUCED
+ gPeiAtaControllerPpiGuid # PPI SOMETIMES_PRODUCED
+ gEfiPeiStallPpiGuid # PPI ALWAYS_PRODUCED
+ gEfiPeiDeviceRecoveryModulePpiGuid # PPI SOMETIMES_CONSUMED
+ gEfiPeiRecoveryModulePpiGuid # PPI SOMETIMES_PRODUCED
+ gEfiPeiResetPpiGuid # PPI ALWAYS_PRODUCED
+ gEfiPeiReadOnlyVariable2PpiGuid # PPI ALWAYS_CONSUMED
+ gEfiPeiBootInRecoveryModePpiGuid # PPI SOMETIMES_PRODUCED
+ gEfiPeiMasterBootModePpiGuid # PPI ALWAYS_PRODUCED
+ gEfiPeiFirmwareVolumeInfoPpiGuid
+ gEfiEndOfPeiSignalPpiGuid
+ gEfiPeiVirtualBlockIoPpiGuid
+ gPeiCapsulePpiGuid # PPI ALWAYS_CONSUMED
+
+[FeaturePcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnFatUsbDisk
+ gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnDataCD
+ gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnFatFloppyDisk
+ gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnIdeDisk
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport
+ gQuarkPlatformTokenSpaceGuid.WaitIfResetDueToError
+
+[Pcd]
+ gQuarkPlatformTokenSpaceGuid.PcdEsramStage1Base
+ gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize
+ gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress
+ gQuarkPlatformTokenSpaceGuid.PcdEccScrubBlkSize
+ gQuarkPlatformTokenSpaceGuid.PcdEccScrubInterval
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ gQuarkPlatformTokenSpaceGuid.PcdFlashQNCMicrocodeSize
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoBaseAddress
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeIoBase
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeIoSize
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartFunctionNumber
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartBusNumber
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartDevNumber
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBusNumber
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioDevNumber
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioFunctionNumber
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBarRegister
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioMmioBase
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohMac0MmioBase
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohMac1MmioBase
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdPeiQNCUsbControllerMemoryBaseAddress
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioBaseAddress
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory32Base
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory32Size
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory64Base
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory64Size
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciExpressSize
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdGbaIoBaseAddress
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkMicrocodeFile
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdTSegSize
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdESramMemorySize
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoverySize
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainSize
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainBase
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadBase
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadSize
+ gQuarkPlatformTokenSpaceGuid.PcdEnableFastBoot
+ gQuarkPlatformTokenSpaceGuid.PcdPlatformType
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac0
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac1
+
+[Depex]
+ gEfiPeiReadOnlyVariable2PpiGuid AND gQNCMemoryInitPpiGuid
diff --git a/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformErratas.c b/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformErratas.c new file mode 100644 index 0000000000..ba8399331a --- /dev/null +++ b/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformErratas.c @@ -0,0 +1,184 @@ +/** @file
+Platform Erratas performed by early init PEIM driver.
+
+Copyright (c) 2013 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CommonHeader.h"
+#include "PlatformEarlyInit.h"
+
+//
+// Constants.
+//
+
+//
+// Platform EHCI Packet Buffer OUT/IN Thresholds, values in number of DWORDs.
+//
+#define EHCI_OUT_THRESHOLD_VALUE (0x7f)
+#define EHCI_IN_THRESHOLD_VALUE (0x7f)
+
+//
+// Platform init USB device interrupt masks.
+//
+#define V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG (0x0000007f)
+#define V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG (B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_OUT_EP_MASK | B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_IN_EP_MASK)
+
+//
+// Global variables defined within this source module.
+//
+
+UINTN IohEhciPciReg[IOH_MAX_EHCI_USB_CONTROLLERS] = {
+ PCI_LIB_ADDRESS (IOH_USB_BUS_NUMBER, IOH_USB_EHCI_DEVICE_NUMBER, IOH_EHCI_FUNCTION_NUMBER, 0),
+};
+
+UINTN IohUsbDevicePciReg[IOH_MAX_USBDEVICE_USB_CONTROLLERS] = {
+ PCI_LIB_ADDRESS (IOH_USB_BUS_NUMBER, IOH_USBDEVICE_DEVICE_NUMBER, IOH_USBDEVICE_FUNCTION_NUMBER, 0),
+};
+
+//
+// Routines local to this source module.
+//
+
+/** Perform USB erratas after MRC init.
+
+**/
+VOID
+PlatformUsbErratasPostMrc (
+ VOID
+ )
+{
+ UINT32 Index;
+ UINT32 TempBar0Addr;
+ UINT16 SaveCmdReg;
+ UINT32 SaveBar0Reg;
+
+ TempBar0Addr = PcdGet32(PcdPeiQNCUsbControllerMemoryBaseAddress);
+
+ //
+ // Apply EHCI controller erratas.
+ //
+ for (Index = 0; Index < IOH_MAX_EHCI_USB_CONTROLLERS; Index++, TempBar0Addr += IOH_USB_CONTROLLER_MMIO_RANGE) {
+
+ if ((PciRead16 (IohEhciPciReg[Index] + R_IOH_USB_VENDOR_ID)) != V_IOH_USB_VENDOR_ID) {
+ continue; // Device not enabled, skip.
+ }
+
+ //
+ // Save current settings for PCI CMD/BAR0 registers
+ //
+ SaveCmdReg = PciRead16 (IohEhciPciReg[Index] + R_IOH_USB_COMMAND);
+ SaveBar0Reg = PciRead32 (IohEhciPciReg[Index] + R_IOH_USB_MEMBAR);
+
+ //
+ // Temp. assign base address register, Enable Memory Space.
+ //
+ PciWrite32 ((IohEhciPciReg[Index] + R_IOH_USB_MEMBAR), TempBar0Addr);
+ PciWrite16 (IohEhciPciReg[Index] + R_IOH_USB_COMMAND, SaveCmdReg | B_IOH_USB_COMMAND_MSE);
+
+
+ //
+ // Set packet buffer OUT/IN thresholds.
+ //
+ MmioAndThenOr32 (
+ TempBar0Addr + R_IOH_EHCI_INSNREG01,
+ (UINT32) (~(B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK | B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK)),
+ (UINT32) ((EHCI_OUT_THRESHOLD_VALUE << B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP) | (EHCI_IN_THRESHOLD_VALUE << B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP))
+ );
+
+ //
+ // Restore settings for PCI CMD/BAR0 registers
+ //
+ PciWrite32 ((IohEhciPciReg[Index] + R_IOH_USB_MEMBAR), SaveBar0Reg);
+ PciWrite16 (IohEhciPciReg[Index] + R_IOH_USB_COMMAND, SaveCmdReg);
+ }
+
+ //
+ // Apply USB device controller erratas.
+ //
+ for (Index = 0; Index < IOH_MAX_USBDEVICE_USB_CONTROLLERS; Index++, TempBar0Addr += IOH_USB_CONTROLLER_MMIO_RANGE) {
+
+ if ((PciRead16 (IohUsbDevicePciReg[Index] + R_IOH_USB_VENDOR_ID)) != V_IOH_USB_VENDOR_ID) {
+ continue; // Device not enabled, skip.
+ }
+
+ //
+ // Save current settings for PCI CMD/BAR0 registers
+ //
+ SaveCmdReg = PciRead16 (IohUsbDevicePciReg[Index] + R_IOH_USB_COMMAND);
+ SaveBar0Reg = PciRead32 (IohUsbDevicePciReg[Index] + R_IOH_USB_MEMBAR);
+
+ //
+ // Temp. assign base address register, Enable Memory Space.
+ //
+ PciWrite32 ((IohUsbDevicePciReg[Index] + R_IOH_USB_MEMBAR), TempBar0Addr);
+ PciWrite16 (IohUsbDevicePciReg[Index] + R_IOH_USB_COMMAND, SaveCmdReg | B_IOH_USB_COMMAND_MSE);
+
+ //
+ // Erratas for USB Device interrupt registers.
+ //
+
+ //
+ // 1st Mask interrupts.
+ //
+ MmioWrite32 (
+ TempBar0Addr + R_IOH_USBDEVICE_D_INTR_MSK_UDC_REG,
+ V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG
+ );
+ //
+ // 2nd RW/1C of equivalent status bits.
+ //
+ MmioWrite32 (
+ TempBar0Addr + R_IOH_USBDEVICE_D_INTR_UDC_REG,
+ V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG
+ );
+
+ //
+ // 1st Mask end point interrupts.
+ //
+ MmioWrite32 (
+ TempBar0Addr + R_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG,
+ V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG
+ );
+ //
+ // 2nd RW/1C of equivalent end point status bits.
+ //
+ MmioWrite32 (
+ TempBar0Addr + R_IOH_USBDEVICE_EP_INTR_UDC_REG,
+ V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG
+ );
+
+ //
+ // Restore settings for PCI CMD/BAR0 registers
+ //
+ PciWrite32 ((IohUsbDevicePciReg[Index] + R_IOH_USB_MEMBAR), SaveBar0Reg);
+ PciWrite16 (IohUsbDevicePciReg[Index] + R_IOH_USB_COMMAND, SaveCmdReg);
+ }
+}
+
+//
+// Routines exported by this source module.
+//
+
+/** Perform Platform Erratas after MRC.
+
+ @retval EFI_SUCCESS Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformErratasPostMrc (
+ VOID
+ )
+{
+ PlatformUsbErratasPostMrc ();
+ return EFI_SUCCESS;
+}
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