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| author | Michael Kubacki <michael.kubacki@microsoft.com> | 2020-04-07 02:34:22 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-04-21 02:20:51 +0000 |
| commit | 6e3c834ae47d1201c4ddcc6a6adc5e44718c7617 (patch) | |
| tree | 050b0f03aada251221ecc0531841d4ef4c4f4f7e /SecurityPkg/Tcg | |
| parent | cda6f9455c87fc8d69283ea83b6ce55a649b28d0 (diff) | |
| download | edk2-6e3c834ae47d1201c4ddcc6a6adc5e44718c7617.tar.gz edk2-6e3c834ae47d1201c4ddcc6a6adc5e44718c7617.tar.bz2 edk2-6e3c834ae47d1201c4ddcc6a6adc5e44718c7617.zip | |
SecurityPkg Tcg: Use SW SMI IO port PCD in Tpm.asl
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2416
Replaces the hardcoded value of 0xB2 with a PCD for the SMI port access
operation region. This allows platforms to customize the IO port value if
necessary.
Cc: Kun Qin <Kun.Qin@microsoft.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Guomin Jiang <guomin.jiang@intel.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
Diffstat (limited to 'SecurityPkg/Tcg')
| -rw-r--r-- | SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.inf | 4 | ||||
| -rw-r--r-- | SecurityPkg/Tcg/Tcg2Smm/Tpm.asl | 18 | ||||
| -rw-r--r-- | SecurityPkg/Tcg/TcgSmm/TcgSmm.inf | 4 | ||||
| -rw-r--r-- | SecurityPkg/Tcg/TcgSmm/Tpm.asl | 17 |
4 files changed, 26 insertions, 17 deletions
diff --git a/SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.inf b/SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.inf index e33cbcc491..2ebf2e05f2 100644 --- a/SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.inf +++ b/SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.inf @@ -21,6 +21,7 @@ # This external input must be validated carefully to avoid security issue.
#
# Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) Microsoft Corporation.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -70,6 +71,9 @@ gEfiSmmVariableProtocolGuid ## CONSUMES
gEfiAcpiTableProtocolGuid ## CONSUMES
+[FixedPcd]
+ gEfiSecurityPkgTokenSpaceGuid.PcdSmiCommandIoPort ## CONSUMES
+
[Pcd]
gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId ## SOMETIMES_CONSUMES
diff --git a/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl b/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl index 7a91708a1a..95f9d7eae8 100644 --- a/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl +++ b/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl @@ -4,7 +4,7 @@ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
(c)Copyright 2016 HP Development Company, L.P.<BR>
-Copyright (c) 2017, Microsoft Corporation. All rights reserved. <BR>
+Copyright (c) Microsoft Corporation.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -41,10 +41,10 @@ DefinitionBlock ( //
// Operational region for Smi port access
//
- OperationRegion (SMIP, SystemIO, 0xB2, 1)
+ OperationRegion (SMIP, SystemIO, FixedPcdGet16 (PcdSmiCommandIoPort), 1)
Field (SMIP, ByteAcc, NoLock, Preserve)
{
- IOB2, 8
+ IOPN, 8
}
//
@@ -258,7 +258,7 @@ DefinitionBlock ( //
// Trigger the SMI interrupt
//
- Store (MCIN, IOB2)
+ Store (MCIN, IOPN)
}
}
Return (0)
@@ -359,7 +359,7 @@ DefinitionBlock ( //
// Trigger the SMI interrupt
//
- Store (PPIN, IOB2)
+ Store (PPIN, IOPN)
Return (FRET)
@@ -390,7 +390,7 @@ DefinitionBlock ( //
// Trigger the SMI interrupt
//
- Store (PPIN, IOB2)
+ Store (PPIN, IOPN)
Store (LPPR, Index (TPM3, 0x01))
Store (PPRP, Index (TPM3, 0x02))
@@ -422,7 +422,7 @@ DefinitionBlock ( //
// Trigger the SMI interrupt
//
- Store (PPIN, IOB2)
+ Store (PPIN, IOPN)
Return (FRET)
}
Case (8)
@@ -436,7 +436,7 @@ DefinitionBlock ( //
// Trigger the SMI interrupt
//
- Store (PPIN, IOB2)
+ Store (PPIN, IOPN)
Return (FRET)
}
@@ -475,7 +475,7 @@ DefinitionBlock ( //
// Trigger the SMI interrupt
//
- Store (MCIN, IOB2)
+ Store (MCIN, IOPN)
Return (MRET)
}
Default {BreakPoint}
diff --git a/SecurityPkg/Tcg/TcgSmm/TcgSmm.inf b/SecurityPkg/Tcg/TcgSmm/TcgSmm.inf index 29f9c15b0e..9fac896dde 100644 --- a/SecurityPkg/Tcg/TcgSmm/TcgSmm.inf +++ b/SecurityPkg/Tcg/TcgSmm/TcgSmm.inf @@ -10,6 +10,7 @@ # This external input must be validated carefully to avoid security issue.
#
# Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) Microsoft Corporation.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -63,6 +64,9 @@ gEfiSmmVariableProtocolGuid ## CONSUMES
gEfiAcpiTableProtocolGuid ## CONSUMES
+[FixedPcd]
+ gEfiSecurityPkgTokenSpaceGuid.PcdSmiCommandIoPort ## CONSUMES
+
[Pcd]
gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId ## SOMETIMES_CONSUMES
diff --git a/SecurityPkg/Tcg/TcgSmm/Tpm.asl b/SecurityPkg/Tcg/TcgSmm/Tpm.asl index 739067dbec..9d5e6ddc11 100644 --- a/SecurityPkg/Tcg/TcgSmm/Tpm.asl +++ b/SecurityPkg/Tcg/TcgSmm/Tpm.asl @@ -3,6 +3,7 @@ and MemoryClear.
Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
+Copyright (c) Microsoft Corporation.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -41,10 +42,10 @@ DefinitionBlock ( //
// Operational region for Smi port access
//
- OperationRegion (SMIP, SystemIO, 0xB2, 1)
+ OperationRegion (SMIP, SystemIO, FixedPcdGet16 (PcdSmiCommandIoPort), 1)
Field (SMIP, ByteAcc, NoLock, Preserve)
{
- IOB2, 8
+ IOPN, 8
}
//
@@ -96,7 +97,7 @@ DefinitionBlock ( //
// Trigger the SMI interrupt
//
- Store (MCIN, IOB2)
+ Store (MCIN, IOPN)
}
}
Return (0)
@@ -196,7 +197,7 @@ DefinitionBlock ( //
// Trigger the SMI interrupt
//
- Store (PPIN, IOB2)
+ Store (PPIN, IOPN)
Return (FRET)
@@ -227,7 +228,7 @@ DefinitionBlock ( //
// Trigger the SMI interrupt
//
- Store (PPIN, IOB2)
+ Store (PPIN, IOPN)
Store (LPPR, Index (TPM3, 0x01))
Store (PPRP, Index (TPM3, 0x02))
@@ -255,7 +256,7 @@ DefinitionBlock ( //
// Trigger the SMI interrupt
//
- Store (PPIN, IOB2)
+ Store (PPIN, IOPN)
Return (FRET)
}
Case (8)
@@ -269,7 +270,7 @@ DefinitionBlock ( //
// Trigger the SMI interrupt
//
- Store (PPIN, IOB2)
+ Store (PPIN, IOPN)
Return (FRET)
}
@@ -308,7 +309,7 @@ DefinitionBlock ( //
// Trigger the SMI interrupt
//
- Store (MCIN, IOB2)
+ Store (MCIN, IOPN)
Return (MRET)
}
Default {BreakPoint}
|