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authorJason <yun.lou@intel.com>2022-01-10 21:52:52 +0800
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>2022-03-01 01:45:47 +0000
commit7bc8b1d9f412507d579f21ea9af56fced81e7827 (patch)
tree662a4df5c85d7e44debc9f13b4213e8a9d844082 /SourceLevelDebugPkg
parentd3febfd9ade35dc552df6b3607c2b15d26b82867 (diff)
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SourceLevelDebugPkg: Replace Opcode with the corresponding instructions.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790 Replace Opcode with the corresponding instructions. The code changes have been verified with CompareBuild.py tool, which can be used to compare the results of two different EDK II builds to determine if they generate the same binaries. (tool link: https://github.com/mdkinney/edk2/tree/sandbox/CompareBuild) Signed-off-by: Jason Lou <yun.lou@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Diffstat (limited to 'SourceLevelDebugPkg')
-rw-r--r--SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/AsmFuncs.nasm6
-rw-r--r--SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/AsmFuncs.nasm6
2 files changed, 6 insertions, 6 deletions
diff --git a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/AsmFuncs.nasm b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/AsmFuncs.nasm
index 912256ba45..b5e5a96e34 100644
--- a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/AsmFuncs.nasm
+++ b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/AsmFuncs.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2010 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -321,7 +321,7 @@ NoExtrPush:
test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.
; edx still contains result from CPUID above
jz .2
- db 0xf, 0xae, 00000111y ;fxsave [edi]
+ fxsave [edi]
.2:
;; save the exception data
@@ -342,7 +342,7 @@ NoExtrPush:
cpuid ; use CPUID to determine if FXSAVE/FXRESTOR are supported
test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
jz .3
- db 0xf, 0xae, 00001110y ; fxrstor [esi]
+ fxrstor [esi]
.3:
add esp, 512
diff --git a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/AsmFuncs.nasm b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/AsmFuncs.nasm
index ccee120ca1..b1019e017b 100644
--- a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/AsmFuncs.nasm
+++ b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/AsmFuncs.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
@@ -293,7 +293,7 @@ NoExtrPush:
rep stosq
pop rcx
mov rdi, rsp
- db 0xf, 0xae, 00000111y ;fxsave [rdi]
+ fxsave [rdi]
;; save the exception data
push qword [rbp + 16]
@@ -314,7 +314,7 @@ NoExtrPush:
add rsp, 8
mov rsi, rsp
- db 0xf, 0xae, 00001110y ; fxrstor [rsi]
+ fxrstor [rsi]
add rsp, 512
;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;