diff options
| author | Tuan Phan <tphan@ventanamicro.com> | 2023-07-14 12:08:24 -0700 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-07-15 14:10:18 +0000 |
| commit | f220dcbba86bfc1222180c61bbd31dd6023433db (patch) | |
| tree | 8664b8b0e32903c179710e7f7018bc45722d1d7f /UefiCpuPkg/CpuDxeRiscV64 | |
| parent | cc13dcc57675695d51efe0d61d772155c601a35b (diff) | |
| download | edk2-f220dcbba86bfc1222180c61bbd31dd6023433db.tar.gz edk2-f220dcbba86bfc1222180c61bbd31dd6023433db.tar.bz2 edk2-f220dcbba86bfc1222180c61bbd31dd6023433db.zip | |
UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
During CpuDxe initialization, MMU will be setup with the highest
mode that HW supports.
Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Diffstat (limited to 'UefiCpuPkg/CpuDxeRiscV64')
| -rw-r--r-- | UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 | ||||
| -rw-r--r-- | UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 | ||||
| -rw-r--r-- | UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 2 |
3 files changed, 11 insertions, 2 deletions
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c index 25fe3f54c3..2af3b62234 100644 --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c @@ -296,8 +296,7 @@ CpuSetMemoryAttributes ( IN UINT64 Attributes
)
{
- DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", __func__));
- return EFI_SUCCESS;
+ return RiscVSetMemoryAttributes (BaseAddress, Length, Attributes);
}
/**
@@ -341,6 +340,12 @@ InitializeCpu ( DisableInterrupts ();
//
+ // Enable MMU
+ //
+ Status = RiscVConfigureMmu ();
+ ASSERT_EFI_ERROR (Status);
+
+ //
// Install Boot protocol
//
Status = gBS->InstallProtocolInterface (
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h index 49f4e11966..68e6d038b6 100644 --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h @@ -15,11 +15,13 @@ #include <Protocol/Cpu.h>
#include <Protocol/RiscVBootProtocol.h>
#include <Library/BaseRiscVSbiLib.h>
+#include <Library/BaseRiscVMmuLib.h>
#include <Library/BaseLib.h>
#include <Library/CpuExceptionHandlerLib.h>
#include <Library/DebugLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiDriverEntryPoint.h>
+#include <Register/RiscV64/RiscVEncoding.h>
/**
Flush CPU data cache. If the instruction cache is fully coherent
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf index e8fa25446a..9d9a5ef8f2 100644 --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf @@ -37,6 +37,8 @@ TimerLib
PeCoffGetEntryPointLib
RiscVSbiLib
+ RiscVMmuLib
+ CacheMaintenanceLib
[Sources]
CpuDxe.c
|