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authorHeinrich Schuchardt <heinrich.schuchardt@canonical.com>2024-09-16 23:12:18 +0200
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>2024-10-04 04:53:21 +0000
commitf8c738577f813bbe6cb017cfbb29b70582ab32b4 (patch)
tree912940249114ed2b0d925ad527a577cbd3cf172e /UefiCpuPkg/CpuDxeRiscV64
parent28dd588ca80c61c4bea9294785d5d884ad3f2c41 (diff)
downloadedk2-f8c738577f813bbe6cb017cfbb29b70582ab32b4.tar.gz
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UefiCpuPkg: RiscV64: initialize FPU
The OpenSSL library uses floating point registers. The is no guarantee that a prior firmware stage has enabled the FPU. Provide a library BaseRiscVFpuLib to * Enable the FPU and set it to state 'dirty'. * Clear the fcsr CSR. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Diffstat (limited to 'UefiCpuPkg/CpuDxeRiscV64')
-rw-r--r--UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c6
-rw-r--r--UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h1
-rw-r--r--UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf1
3 files changed, 8 insertions, 0 deletions
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
index c6bae100a9..6a22e01711 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
@@ -360,6 +360,12 @@ InitializeCpu (
ASSERT_EFI_ERROR (Status);
//
+ // Initialize FPU
+ //
+ Status = RiscVInitializeFpu ();
+ ASSERT_EFI_ERROR (Status);
+
+ //
// Install Boot protocol
//
Status = gBS->InstallProtocolInterface (
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
index d4d67778eb..40077d65bd 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
@@ -14,6 +14,7 @@
#include <Protocol/Cpu.h>
#include <Protocol/RiscVBootProtocol.h>
+#include <Library/BaseRiscVFpuLib.h>
#include <Library/BaseRiscVSbiLib.h>
#include <Library/BaseRiscVMmuLib.h>
#include <Library/BaseLib.h>
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
index 9d9a5ef8f2..cb0f71e42e 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
@@ -38,6 +38,7 @@
PeCoffGetEntryPointLib
RiscVSbiLib
RiscVMmuLib
+ RiscVFpuLib
CacheMaintenanceLib
[Sources]