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| author | Michael Kinney <michael.d.kinney@intel.com> | 2016-12-06 23:22:24 -0800 |
|---|---|---|
| committer | Feng Tian <feng.tian@intel.com> | 2016-12-19 09:32:27 +0800 |
| commit | a03bb3d2a9f7486f3bd9539cd35561661c5b38a2 (patch) | |
| tree | ccbff4e64f84e72915a559767a64e271a1edc1ce /UefiCpuPkg/Include/Register | |
| parent | 5f16ecdb023d16229efacfd17058ea4e373a5947 (diff) | |
| download | edk2-a03bb3d2a9f7486f3bd9539cd35561661c5b38a2.tar.gz edk2-a03bb3d2a9f7486f3bd9539cd35561661c5b38a2.tar.bz2 edk2-a03bb3d2a9f7486f3bd9539cd35561661c5b38a2.zip | |
UefiCpuPkg/Include: Update MSEG structure comments
Add comments to describe fields of MSEG_HEADER and
add define values for the MonitorFeatures field.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Diffstat (limited to 'UefiCpuPkg/Include/Register')
| -rw-r--r-- | UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 25 |
1 files changed, 22 insertions, 3 deletions
diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h index af3f39de94..633e54d4e0 100644 --- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h +++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h @@ -520,7 +520,19 @@ typedef union { field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.
**/
typedef struct {
+ ///
+ /// Different processors may use different MSEG revision identifiers. These
+ /// identifiers enable software to avoid using an MSEG header formatted for
+ /// one processor on a processor that uses a different format. Software can
+ /// discover the MSEG revision identifier that a processor uses by reading
+ /// the VMX capability MSR IA32_VMX_MISC.
+ //
UINT32 MsegHeaderRevision;
+ ///
+ /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field
+ /// is the IA-32e mode SMM feature bit. It indicates whether the logical
+ /// processor will be in IA-32e mode after the STM is activated.
+ ///
UINT32 MonitorFeatures;
UINT32 GdtrLimit;
UINT32 GdtrBaseOffset;
@@ -528,12 +540,19 @@ typedef struct { UINT32 EipOffset;
UINT32 EspOffset;
UINT32 Cr3Offset;
- //
- // Pad header so total size is 2KB
- //
+ ///
+ /// Pad header so total size is 2KB
+ ///
UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];
} MSEG_HEADER;
+///
+/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER
+///
+#define STM_FEATURES_IA32E 0x1
+///
+/// @}
+///
/**
Base address of the logical processor's SMRAM image (RO, SMM only). If
|