UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSRs.

Changes includes: 1. Add new MSR definitions. 2. Add support platform info. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
author: Eric Dong <eric.dong@intel.com> 2018-08-30 14:22:09 +0800
committer: Eric Dong <eric.dong@intel.com> 2018-09-26 15:17:12 +0800
commit: 3add020579e77968a3ce9e9620136df46d22e598 (patch)
tree: 72f10482be6c64fc27a677d4d8be20a1c039a888 /UefiCpuPkg/Include
parent: dfb208511e5770d6d0947fb9d6faa1d52a81cc9a (diff)
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1 files changed, 1546 insertions, 1 deletions
diff --git a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
index 866fe30f05..a85997f3e9 100644
--- a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
@@ -39,7 +39,11 @@
   (DisplayFamily == 0x06 && \
    (                        \
     DisplayModel == 0x4E || \
-    DisplayModel == 0x5E    \
+    DisplayModel == 0x5E || \
+    DisplayModel == 0x55 || \
+    DisplayModel == 0x8E || \
+    DisplayModel == 0x9E || \
+    DisplayModel == 0x66    \
     )                       \
    )
 
@@ -125,6 +129,74 @@ typedef union {
 
 
 /**
+  Core. Power Control Register See http://biosbits.org.
+
+  @param  ECX  MSR_SKYLAKE_POWER_CTL (0x000001FC)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_POWER_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_POWER_CTL);
+  AsmWriteMsr64 (MSR_SKYLAKE_POWER_CTL, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_POWER_CTL                     0x000001FC
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_POWER_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the CPU
+    /// to switch to the Minimum Enhanced Intel SpeedStep Technology operating
+    /// point when all execution cores enter MWAIT (C1).
+    ///
+    UINT32  C1EEnable:1;
+    UINT32  Reserved2:17;
+    ///
+    /// [Bit 19] Disable Race to Halt Optimization (R/W) Setting this bit
+    /// disables the Race to Halt optimization and avoids this optimization
+    /// limitation to execute below the most efficient frequency ratio.
+    /// Default value is 0 for processors that support Race to Halt
+    /// optimization. Default value is 1 for processors that do not support
+    /// Race to Halt optimization.
+    ///
+    UINT32  Fix_Me_1:1;
+    ///
+    /// [Bit 20] Disable Energy Efficiency Optimization (R/W) Setting this bit
+    /// disables the P-States energy efficiency optimization. Default value is
+    /// 0. Disable/enable the energy efficiency optimization in P-State legacy
+    /// mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the
+    /// turbo range or into PERF_MIN_CTL value if it is not zero set. In HWP
+    /// mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect between the OS
+    /// desired or OS maximize to the OS minimize performance setting.
+    ///
+    UINT32  DisableEnergyEfficiencyOptimization:1;
+    UINT32  Reserved3:11;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_POWER_CTL_REGISTER;
+
+
+/**
   Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of
   an 128-bit external entropy value for key derivation of an enclave.
 
@@ -2254,4 +2326,1477 @@ typedef union {
   UINT64  Uint64;
 } MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER;
 
+
+/**
+  Package. NPK Address Used by AET Messages (R/W).
+
+  @param  ECX  MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE (0x00000080)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE);
+  AsmWriteMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE   0x00000080
+
+/**
+  MSR information returned for MSR index
+  #MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Lock Bit If set, this MSR cannot be re-written anymore. Lock
+    /// bit has to be set in order for the AET packets to be directed to NPK
+    /// MMIO.
+    ///
+    UINT32  Fix_Me_1:1;
+    UINT32  Reserved:17;
+    ///
+    /// [Bits 31:18] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.
+    ///
+    UINT32  ACPIBAR_BASE_ADDRESS:14;
+    ///
+    /// [Bits 63:32] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.
+    ///
+    UINT32  Fix_Me_2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER;
+
+
+/**
+  Core. Processor Reserved Memory Range Register - Physical Base Control
+  Register (R/W).
+
+  @param  ECX  MSR_SKYLAKE_PRMRR_PHYS_BASE (0x000001F4)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE);
+  AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_PRMRR_PHYS_BASE              0x000001F4
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_BASE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] MemType PRMRR BASE MemType.
+    ///
+    UINT32  MemTypePRMRRBASEMemType:3;
+    UINT32  Reserved1:9;
+    ///
+    /// [Bits 31:12] Base PRMRR Base Address.
+    ///
+    UINT32  BasePRMRRBaseAddress:20;
+    ///
+    /// [Bits 45:32] Base PRMRR Base Address.
+    ///
+    UINT32  Fix_Me_1:14;
+    UINT32  Reserved2:18;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER;
+
+
+/**
+  Core. Processor Reserved Memory Range Register - Physical Mask Control
+  Register (R/W).
+
+  @param  ECX  MSR_SKYLAKE_PRMRR_PHYS_MASK (0x000001F5)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK);
+  AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_PRMRR_PHYS_MASK              0x000001F5
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_MASK
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:10;
+    ///
+    /// [Bit 10] Lock Lock bit for the PRMRR.
+    ///
+    UINT32  Fix_Me_1:1;
+    ///
+    /// [Bit 11] VLD Enable bit for the PRMRR.
+    ///
+    UINT32  VLD:1;
+    ///
+    /// [Bits 31:12] Mask PRMRR MASK bits.
+    ///
+    UINT32  Fix_Me_2:20;
+    ///
+    /// [Bits 45:32] Mask PRMRR MASK bits.
+    ///
+    UINT32  Fix_Me_3:14;
+    UINT32  Reserved2:18;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER;
+
+
+/**
+  Core. Valid PRMRR Configurations (R/W).
+
+  @param  ECX  MSR_SKYLAKE_PRMRR_VALID_CONFIG (0x000001FB)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG);
+  AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_PRMRR_VALID_CONFIG           0x000001FB
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_VALID_CONFIG
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] 1M supported MEE size.
+    ///
+    UINT32  Fix_Me_1:1;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bit 5] 32M supported MEE size.
+    ///
+    UINT32  Fix_Me_2:1;
+    ///
+    /// [Bit 6] 64M supported MEE size.
+    ///
+    UINT32  Fix_Me_3:1;
+    ///
+    /// [Bit 7] 128M supported MEE size.
+    ///
+    UINT32  Fix_Me_4:1;
+    UINT32  Reserved2:24;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER;
+
+
+/**
+  Package. (R/W) The PRMRR range is used to protect Xucode memory from
+  unauthorized reads and writes. Any IO access to this range is aborted. This
+  register controls the location of the PRMRR range by indicating its starting
+  address. It functions in tandem with the PRMRR mask register.
+
+  @param  ECX  MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE (0x000002F4)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE       0x000002F4
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:12;
+    ///
+    /// [Bits 31:12] Range Base This field corresponds to bits 38:12 of the
+    /// base address memory range which is allocated to PRMRR memory.
+    ///
+    UINT32  Fix_Me_1:20;
+    ///
+    /// [Bits 38:32] Range Base This field corresponds to bits 38:12 of the
+    /// base address memory range which is allocated to PRMRR memory.
+    ///
+    UINT32  Fix_Me_2:7;
+    UINT32  Reserved2:25;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER;
+
+
+/**
+  Package. (R/W) This register controls the size of the PRMRR range by
+  indicating which address bits must match the PRMRR base register value.
+
+  @param  ECX  MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK (0x000002F5)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK       0x000002F5
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:10;
+    ///
+    /// [Bit 10] Lock Setting this bit locks all writeable settings in this
+    /// register, including itself.
+    ///
+    UINT32  Fix_Me_1:1;
+    ///
+    /// [Bit 11] Range_En Indicates whether the PRMRR range is enabled and
+    /// valid.
+    ///
+    UINT32  Fix_Me_2:1;
+    UINT32  Reserved2:20;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER;
+
+/**
+  Package. Ring Ratio Limit (R/W) This register provides Min/Max Ratio Limits
+  for the LLC and Ring.
+
+  @param  ECX  MSR_SKYLAKE_RING_RATIO_LIMIT (0x00000620)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT);
+  AsmWriteMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_RING_RATIO_LIMIT             0x00000620
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_RING_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 6:0] MAX_Ratio This field is used to limit the max ratio of the
+    /// LLC/Ring.
+    ///
+    UINT32  Fix_Me_1:7;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bits 14:8] MIN_Ratio Writing to this field controls the minimum
+    /// possible ratio of the LLC/Ring.
+    ///
+    UINT32  Fix_Me_2:7;
+    UINT32  Reserved2:17;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Branch Monitoring Global Control (R/W).
+
+  @param  ECX  MSR_SKYLAKE_BR_DETECT_CTRL (0x00000350)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL);
+  AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_BR_DETECT_CTRL               0x00000350
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_CTRL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] EnMonitoring Global enable for branch monitoring.
+    ///
+    UINT32  EnMonitoring:1;
+    ///
+    /// [Bit 1] EnExcept Enable branch monitoring event signaling on threshold
+    /// trip. The branch monitoring event handler is signaled via the existing
+    /// PMI signaling mechanism as programmed from the corresponding local
+    /// APIC LVT entry.
+    ///
+    UINT32  EnExcept:1;
+    ///
+    /// [Bit 2] EnLBRFrz Enable LBR freeze on threshold trip. This will cause
+    /// the LBR frozen bit 58 to be set in IA32_PERF_GLOBAL_STATUS when a
+    /// triggering condition occurs and this bit is enabled.
+    ///
+    UINT32  EnLBRFrz:1;
+    ///
+    /// [Bit 3] DisableInGuest When set to '1', branch monitoring, event
+    /// triggering and LBR freeze actions are disabled when operating at VMX
+    /// non-root operation.
+    ///
+    UINT32  DisableInGuest:1;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 17:8] WindowSize Window size defined by WindowCntSel. Values 0 -
+    /// 1023 are supported. Once the Window counter reaches the WindowSize
+    /// count both the Window Counter and all Branch Monitoring Counters are
+    /// cleared.
+    ///
+    UINT32  WindowSize:10;
+    UINT32  Reserved2:6;
+    ///
+    /// [Bits 25:24] WindowCntSel Window event count select: '00 =
+    /// Instructions retired. '01 = Branch instructions retired '10 = Return
+    /// instructions retired. '11 = Indirect branch instructions retired.
+    ///
+    UINT32  WindowCntSel:2;
+    ///
+    /// [Bit 26] CntAndMode When set to '1', the overall branch monitoring
+    /// event triggering condition is true only if all enabled counters'
+    /// threshold conditions are true. When '0', the threshold tripping
+    /// condition is true if any enabled counters' threshold is true.
+    ///
+    UINT32  CntAndMode:1;
+    UINT32  Reserved3:5;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER;
+
+/**
+  Branch Monitoring Global Status (R/W).
+
+  @param  ECX  MSR_SKYLAKE_BR_DETECT_STATUS (0x00000351)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS);
+  AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_BR_DETECT_STATUS             0x00000351
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Branch Monitoring Event Signaled When set to '1', Branch
+    /// Monitoring event signaling is blocked until this bit is cleared by
+    /// software.
+    ///
+    UINT32  BranchMonitoringEventSignaled:1;
+    ///
+    /// [Bit 1] LBRsValid This status bit is set to '1' if the LBR state is
+    /// considered valid for sampling by branch monitoring software.
+    ///
+    UINT32  LBRsValid:1;
+    UINT32  Reserved1:6;
+    ///
+    /// [Bit 8] CntrHit0 Branch monitoring counter #0 threshold hit. This
+    /// status bit is sticky and once set requires clearing by software.
+    /// Counter operation continues independent of the state of the bit.
+    ///
+    UINT32  CntrHit0:1;
+    ///
+    /// [Bit 9] CntrHit1 Branch monitoring counter #1 threshold hit. This
+    /// status bit is sticky and once set requires clearing by software.
+    /// Counter operation continues independent of the state of the bit.
+    ///
+    UINT32  CntrHit1:1;
+    UINT32  Reserved2:6;
+    ///
+    /// [Bits 25:16] CountWindow The current value of the window counter. The
+    /// count value is frozen on a valid branch monitoring triggering
+    /// condition. This is a 10-bit unsigned value.
+    ///
+    UINT32  CountWindow:10;
+    UINT32  Reserved3:6;
+    ///
+    /// [Bits 39:32] Count0 The current value of counter 0 updated after each
+    /// occurrence of the event being counted. The count value is frozen on a
+    /// valid branch monitoring triggering condition (in which case CntrHit0
+    /// will also be set). This is an 8-bit signed value (2's complement).
+    /// Heuristic events which only increment will saturate and freeze at
+    /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum
+    /// value 0x7F (+127) and minimum value 0x80 (-128).
+    ///
+    UINT32  Count0:8;
+    ///
+    /// [Bits 47:40] Count1 The current value of counter 1 updated after each
+    /// occurrence of the event being counted. The count value is frozen on a
+    /// valid branch monitoring triggering condition (in which case CntrHit1
+    /// will also be set). This is an 8-bit signed value (2's complement).
+    /// Heuristic events which only increment will saturate and freeze at
+    /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum
+    /// value 0x7F (+127) and minimum value 0x80 (-128).
+    ///
+    UINT32  Count1:8;
+    UINT32  Reserved4:16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER;
+
+
+/**
+  Package. Package C3 Residency Counter (R/O). Note: C-state values are
+  processor specific C-state code names, unrelated to MWAIT extension C-state
+  parameters or ACPI C-states.
+
+  @param  ECX  MSR_SKYLAKE_PKG_C3_RESIDENCY (0x000003F8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_C3_RESIDENCY);
+  @endcode
+**/
+#define MSR_SKYLAKE_PKG_C3_RESIDENCY             0x000003F8
+
+
+/**
+  Core. Core C1 Residency Counter (R/O). Value since last reset for the Core
+  C1 residency. Counter rate is the Max Non-Turbo frequency (same as TSC).
+  This counter counts in case both of the core's threads are in an idle state
+  and at least one of the core's thread residency is in a C1 state or in one
+  of its sub states. The counter is updated only after a core C state exit.
+  Note: Always reads 0 if core C1 is unsupported. A value of zero indicates
+  that this processor does not support core C1 or never entered core C1 level
+  state.
+
+  @param  ECX  MSR_SKYLAKE_CORE_C1_RESIDENCY (0x00000660)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C1_RESIDENCY);
+  @endcode
+**/
+#define MSR_SKYLAKE_CORE_C1_RESIDENCY            0x00000660
+
+
+/**
+  Core. Core C3 Residency Counter (R/O). Will always return 0.
+
+  @param  ECX  MSR_SKYLAKE_CORE_C3_RESIDENCY (0x00000662)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C3_RESIDENCY);
+  @endcode
+**/
+#define MSR_SKYLAKE_CORE_C3_RESIDENCY            0x00000662
+
+
+/**
+  Package. Protected Processor Inventory Number Enable Control (R/W).
+
+  @param  ECX  MSR_SKYLAKE_PPIN_CTL (0x0000004E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_PPIN_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PPIN_CTL);
+  AsmWriteMsr64 (MSR_SKYLAKE_PPIN_CTL, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_PPIN_CTL                     0x0000004E
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_PPIN_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] LockOut (R/WO) See Table 2-25.
+    ///
+    UINT32  LockOut:1;
+    ///
+    /// [Bit 1] Enable_PPIN (R/W) See Table 2-25.
+    ///
+    UINT32  Enable_PPIN:1;
+    UINT32  Reserved1:30;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_PPIN_CTL_REGISTER;
+
+
+/**
+  Package. Protected Processor Inventory Number (R/O). Protected Processor
+  Inventory Number (R/O) See Table 2-25.
+
+  @param  ECX  MSR_SKYLAKE_PPIN (0x0000004F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_PPIN);
+  @endcode
+**/
+#define MSR_SKYLAKE_PPIN                         0x0000004F
+
+
+/**
+  Package. Platform Information Contains power management and other model
+  specific features enumeration. See http://biosbits.org.
+
+  @param  ECX  MSR_SKYLAKE_PLATFORM_INFO (0x000000CE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_PLATFORM_INFO                0x000000CE
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.
+    ///
+    UINT32  MaximumNon_TurboRatio:8;
+    UINT32  Reserved2:7;
+    ///
+    /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.
+    ///
+    UINT32  PPIN_CAP:1;
+    UINT32  Reserved3:4;
+    ///
+    /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See
+    /// Table 2-25.
+    ///
+    UINT32  ProgrammableRatioLimit:1;
+    ///
+    /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See
+    /// Table 2-25.
+    ///
+    UINT32  ProgrammableTDPLimit:1;
+    ///
+    /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.
+    ///
+    UINT32  ProgrammableTJOFFSET:1;
+    UINT32  Reserved4:1;
+    UINT32  Reserved5:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.
+    ///
+    UINT32  MaximumEfficiencyRatio:8;
+    UINT32  Reserved6:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_PLATFORM_INFO_REGISTER;
+
+
+/**
+  Core. C-State Configuration Control (R/W) Note: C-state values are processor
+  specific C-state code names, unrelated to MWAIT extension C-state parameters
+  or ACPI C-states. `See http://biosbits.org. <http://biosbits.org/>`__.
+
+  @param  ECX  MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL (0x000000E2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL);
+  AsmWriteMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL       0x000000E2
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
+    /// processor-specific C-state code name (consuming the least power) for
+    /// the package. The default is set as factory-configured package Cstate
+    /// limit. The following C-state code name encodings are supported: 000b:
+    /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)
+    /// 011b: C6 (retention) 111b: No Package C state limits. All C states
+    /// supported by the processor are available.
+    ///
+    UINT32  C_StateLimit:3;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
+    ///
+    UINT32  MWAITRedirectionEnable:1;
+    UINT32  Reserved2:4;
+    ///
+    /// [Bit 15] CFG Lock (R/WO).
+    ///
+    UINT32  CFGLock:1;
+    ///
+    /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor
+    /// will convert HALT or MWAT(C1) to MWAIT(C6).
+    ///
+    UINT32  AutomaticC_StateConversionEnable:1;
+    UINT32  Reserved3:8;
+    ///
+    /// [Bit 25] C3 State Auto Demotion Enable (R/W).
+    ///
+    UINT32  C3StateAutoDemotionEnable:1;
+    ///
+    /// [Bit 26] C1 State Auto Demotion Enable (R/W).
+    ///
+    UINT32  C1StateAutoDemotionEnable:1;
+    ///
+    /// [Bit 27] Enable C3 Undemotion (R/W).
+    ///
+    UINT32  EnableC3Undemotion:1;
+    ///
+    /// [Bit 28] Enable C1 Undemotion (R/W).
+    ///
+    UINT32  EnableC1Undemotion:1;
+    ///
+    /// [Bit 29] Package C State Demotion Enable (R/W).
+    ///
+    UINT32  CStateDemotionEnable:1;
+    ///
+    /// [Bit 30] Package C State UnDemotion Enable (R/W).
+    ///
+    UINT32  CStateUnDemotionEnable:1;
+    UINT32  Reserved4:1;
+    UINT32  Reserved5:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER;
+
+
+/**
+  Thread. Global Machine Check Capability (R/O).
+
+  @param  ECX  MSR_SKYLAKE_IA32_MCG_CAP (0x00000179)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_IA32_MCG_CAP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_MCG_CAP);
+  @endcode
+**/
+#define MSR_SKYLAKE_IA32_MCG_CAP                 0x00000179
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_IA32_MCG_CAP
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Count.
+    ///
+    UINT32  Count:8;
+    ///
+    /// [Bit 8] MCG_CTL_P.
+    ///
+    UINT32  MCG_CTL_P:1;
+    ///
+    /// [Bit 9] MCG_EXT_P.
+    ///
+    UINT32  MCG_EXT_P:1;
+    ///
+    /// [Bit 10] MCP_CMCI_P.
+    ///
+    UINT32  MCP_CMCI_P:1;
+    ///
+    /// [Bit 11] MCG_TES_P.
+    ///
+    UINT32  MCG_TES_P:1;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 23:16] MCG_EXT_CNT.
+    ///
+    UINT32  MCG_EXT_CNT:8;
+    ///
+    /// [Bit 24] MCG_SER_P.
+    ///
+    UINT32  MCG_SER_P:1;
+    ///
+    /// [Bit 25] MCG_EM_P.
+    ///
+    UINT32  MCG_EM_P:1;
+    ///
+    /// [Bit 26] MCG_ELOG_P.
+    ///
+    UINT32  MCG_ELOG_P:1;
+    UINT32  Reserved2:5;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_IA32_MCG_CAP_REGISTER;
+
+
+/**
+  THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
+  Enhancement. Accessible only while in SMM.
+
+  @param  ECX  MSR_SKYLAKE_SMM_MCA_CAP (0x0000017D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_SMM_MCA_CAP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_SMM_MCA_CAP);
+  AsmWriteMsr64 (MSR_SKYLAKE_SMM_MCA_CAP, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_SMM_MCA_CAP                  0x0000017D
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_SMM_MCA_CAP
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    UINT32  Reserved2:26;
+    ///
+    /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
+    /// SMM code access restriction is supported and a host-space interface is
+    /// available to SMM handler.
+    ///
+    UINT32  SMM_Code_Access_Chk:1;
+    ///
+    /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
+    /// SMM long flow indicator is supported and a host-space interface is
+    /// available to SMM handler.
+    ///
+    UINT32  Long_Flow_Indication:1;
+    UINT32  Reserved3:4;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_SMM_MCA_CAP_REGISTER;
+
+
+/**
+  Package. Temperature Target.
+
+  @param  ECX  MSR_SKYLAKE_TEMPERATURE_TARGET (0x000001A2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET);
+  AsmWriteMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_TEMPERATURE_TARGET           0x000001A2
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_TEMPERATURE_TARGET
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:16;
+    ///
+    /// [Bits 23:16] Temperature Target (RO) See Table 2-25.
+    ///
+    UINT32  TemperatureTarget:8;
+    ///
+    /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.
+    ///
+    UINT32  TCCActivationOffset:4;
+    UINT32  Reserved2:4;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER;
+
+/**
+  Package. This register defines the active core ranges for each frequency
+  point. NUMCORE[0:7] must be populated in ascending order. NUMCORE[i+1] must
+  be greater than NUMCORE[i]. Entries with NUMCORE[i] == 0 will be ignored.
+  The last valid entry must have NUMCORE >= the number of cores in the SKU. If
+  any of the rules above are broken, the configuration is silently rejected.
+
+  @param  ECX  MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES (0x000001AE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES);
+  AsmWriteMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES      0x000001AE
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] NUMCORE_0 Defines the active core ranges for each frequency
+    /// point.
+    ///
+    UINT32  NUMCORE_0:8;
+    ///
+    /// [Bits 15:8] NUMCORE_1 Defines the active core ranges for each
+    /// frequency point.
+    ///
+    UINT32  NUMCORE_1:8;
+    ///
+    /// [Bits 23:16] NUMCORE_2 Defines the active core ranges for each
+    /// frequency point.
+    ///
+    UINT32  NUMCORE_2:8;
+    ///
+    /// [Bits 31:24] NUMCORE_3 Defines the active core ranges for each
+    /// frequency point.
+    ///
+    UINT32  NUMCORE_3:8;
+    ///
+    /// [Bits 39:32] NUMCORE_4 Defines the active core ranges for each
+    /// frequency point.
+    ///
+    UINT32  NUMCORE_4:8;
+    ///
+    /// [Bits 47:40] NUMCORE_5 Defines the active core ranges for each
+    /// frequency point.
+    ///
+    UINT32  NUMCORE_5:8;
+    ///
+    /// [Bits 55:48] NUMCORE_6 Defines the active core ranges for each
+    /// frequency point.
+    ///
+    UINT32  NUMCORE_6:8;
+    ///
+    /// [Bits 63:56] NUMCORE_7 Defines the active core ranges for each
+    /// frequency point.
+    ///
+    UINT32  NUMCORE_7:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER;
+
+
+/**
+  Package. Unit Multipliers Used in RAPL Interfaces (R/O).
+
+  @param  ECX  MSR_SKYLAKE_RAPL_POWER_UNIT (0x00000606)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RAPL_POWER_UNIT);
+  @endcode
+**/
+#define MSR_SKYLAKE_RAPL_POWER_UNIT              0x00000606
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_RAPL_POWER_UNIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
+    ///
+    UINT32  PowerUnits:4;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 12:8] Package. Energy Status Units Energy related information
+    /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
+    /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
+    /// micro-joules).
+    ///
+    UINT32  EnergyStatusUnits:5;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
+    /// Interfaces.".
+    ///
+    UINT32  TimeUnits:4;
+    UINT32  Reserved3:12;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER;
+
+
+/**
+  Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
+  Domain.".
+
+  @param  ECX  MSR_SKYLAKE_DRAM_POWER_LIMIT (0x00000618)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT, Msr);
+  @endcode
+**/
+#define MSR_SKYLAKE_DRAM_POWER_LIMIT             0x00000618
+
+
+/**
+  Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.
+
+  @param  ECX  MSR_SKYLAKE_DRAM_ENERGY_STATUS (0x00000619)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_DRAM_ENERGY_STATUS);
+  @endcode
+**/
+#define MSR_SKYLAKE_DRAM_ENERGY_STATUS           0x00000619
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_DRAM_ENERGY_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration
+    /// to enable DRAM RAPL mode 0 (Direct VR).
+    ///
+    UINT32  Energy:32;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER;
+
+
+/**
+  Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
+  RAPL Domain.".
+
+  @param  ECX  MSR_SKYLAKE_DRAM_PERF_STATUS (0x0000061B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_PERF_STATUS);
+  @endcode
+**/
+#define MSR_SKYLAKE_DRAM_PERF_STATUS             0x0000061B
+
+
+/**
+  Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
+
+  @param  ECX  MSR_SKYLAKE_DRAM_POWER_INFO (0x0000061C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO);
+  AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO, Msr);
+  @endcode
+**/
+#define MSR_SKYLAKE_DRAM_POWER_INFO              0x0000061C
+
+
+/**
+  Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
+  fields represent the widest possible range of uncore frequencies. Writing to
+  these fields allows software to control the minimum and the maximum
+  frequency that hardware will select.
+
+  @param  ECX  MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT (0x00000620)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT);
+  AsmWriteMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT        0x00000620
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
+    /// LLC/Ring.
+    ///
+    UINT32  MAX_RATIO:7;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
+    /// possible ratio of the LLC/Ring.
+    ///
+    UINT32  MIN_RATIO:7;
+    UINT32  Reserved2:17;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Package. Reserved (R/O) Reads return 0.
+
+  @param  ECX  MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);
+  @endcode
+**/
+#define MSR_SKYLAKE_PP0_ENERGY_STATUS            0x00000639
+
+
+/**
+  THREAD. Monitoring Event Select Register (R/W) If CPUID.(EAX=07H,
+  ECX=0):EBX.RDT-M[bit 12] = 1.
+
+  @param  ECX  MSR_SKYLAKE_IA32_QM_EVTSEL (0x00000C8D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL);
+  AsmWriteMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_IA32_QM_EVTSEL               0x00000C8D
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_IA32_QM_EVTSEL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] EventID (RW) Event encoding: 0x00: No monitoring. 0x01: L3
+    /// occupancy monitoring. 0x02: Total memory bandwidth monitoring. 0x03:
+    /// Local memory bandwidth monitoring. All other encoding reserved.
+    ///
+    UINT32  EventID:8;
+    UINT32  Reserved1:24;
+    ///
+    /// [Bits 41:32] RMID (RW).
+    ///
+    UINT32  RMID:10;
+    UINT32  Reserved2:22;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER;
+
+
+/**
+  THREAD. Resource Association Register (R/W).
+
+  @param  ECX  MSR_SKYLAKE_IA32_PQR_ASSOC (0x00000C8F)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC);
+  AsmWriteMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_IA32_PQR_ASSOC               0x00000C8F
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_IA32_PQR_ASSOC
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 9:0] RMID.
+    ///
+    UINT32  RMID:10;
+    UINT32  Reserved1:22;
+    ///
+    /// [Bits 51:32] COS (R/W).
+    ///
+    UINT32  COS:20;
+    UINT32  Reserved2:12;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER;
+
+
+/**
+  Package. L3 Class Of Service Mask - COS N (R/W) If CPUID.(EAX=10H,
+  ECX=1):EDX.COS_MAX[15:0] >=0.
+
+  @param  ECX  MSR_SKYLAKE_IA32_L3_QOS_MASK_N
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N);
+  AsmWriteMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_0           0x00000C90
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_1           0x00000C91
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_2           0x00000C92
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_3           0x00000C93
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_4           0x00000C94
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_5           0x00000C95
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_6           0x00000C96
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_7           0x00000C97
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_8           0x00000C98
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_9           0x00000C99
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_10          0x00000C9A
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_11          0x00000C9B
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_12          0x00000C9C
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_13          0x00000C9D
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_14          0x00000C9E
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_15          0x00000C9F
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_IA32_L3_QOS_MASK_N
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 19:0] CBM: Bit vector of available L3 ways for COS N enforcement.
+    ///
+    UINT32  CBM:20;
+    UINT32  Reserved2:12;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER;
+
+
 #endif
author	Eric Dong <eric.dong@intel.com>	2018-08-30 14:22:09 +0800
committer	Eric Dong <eric.dong@intel.com>	2018-09-26 15:17:12 +0800
commit	3add020579e77968a3ce9e9620136df46d22e598 (patch)
tree	72f10482be6c64fc27a677d4d8be20a1c039a888 /UefiCpuPkg/Include
parent	dfb208511e5770d6d0947fb9d6faa1d52a81cc9a (diff)
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