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| author | Ray Ni <ray.ni@intel.com> | 2019-04-08 15:32:00 +0800 |
|---|---|---|
| committer | Ray Ni <ray.ni@intel.com> | 2019-04-09 09:12:22 +0800 |
| commit | f8113e25001e715390127f23e2197252cbd6d1a2 (patch) | |
| tree | e5d1eb0e7f114562f2c8d7c2e1e817ac7a5911e0 /UefiCpuPkg/Include | |
| parent | 7f33d4f22836226a6a86c3112ac6fcb2f1209152 (diff) | |
| download | edk2-f8113e25001e715390127f23e2197252cbd6d1a2.tar.gz edk2-f8113e25001e715390127f23e2197252cbd6d1a2.tar.bz2 edk2-f8113e25001e715390127f23e2197252cbd6d1a2.zip | |
UefiCpuPkg/Cpuid.h: Update CPUID.7H.ECX structure for 5-level paging
Reserved6 is changed to Reserved7 because the bit width is changed.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Diffstat (limited to 'UefiCpuPkg/Include')
| -rw-r--r-- | UefiCpuPkg/Include/Register/Cpuid.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/UefiCpuPkg/Include/Register/Cpuid.h b/UefiCpuPkg/Include/Register/Cpuid.h index e0f4f968f4..a67f2a1dff 100644 --- a/UefiCpuPkg/Include/Register/Cpuid.h +++ b/UefiCpuPkg/Include/Register/Cpuid.h @@ -1506,8 +1506,11 @@ typedef union { /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).
///
UINT32 AVX512_VPOPCNTDQ:1;
- UINT32 Reserved6:2;
-
+ UINT32 Reserved7:1;
+ ///
+ /// [Bits 16] Supports 5-level paging if 1.
+ ///
+ UINT32 FiveLevelPage:1;
///
/// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions
/// in 64-bit mode.
|