UefiCpuPkg: Clean up source files

1. Do not use tab characters
2. No trailing white space in one line
3. All files must end with CRLF

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>

3 files changed, 37 insertions, 37 deletions

diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index 3045035020..6b89faf3df 100644
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -4,7 +4,7 @@
   This local APIC library instance supports x2APIC capable processors

   which have xAPIC and x2APIC modes.

 

-  Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>

   Copyright (c) 2017, AMD Inc. All rights reserved.<BR>

 

   This program and the accompanying materials

@@ -69,12 +69,12 @@ LocalApicBaseAddressMsrSupported (
 {

   UINT32  RegEax;

   UINTN   FamilyId;

-  

+

   AsmCpuid (1, &RegEax, NULL, NULL, NULL);

   FamilyId = BitFieldRead32 (RegEax, 8, 11);

   if (FamilyId == 0x04 || FamilyId == 0x05) {

     //

-    // CPUs with a FamilyId of 0x04 or 0x05 do not support the 

+    // CPUs with a FamilyId of 0x04 or 0x05 do not support the

     // Local APIC Base Address MSR

     //

     return FALSE;

@@ -105,7 +105,7 @@ GetLocalApicBaseAddress (
   }

 

   ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);

-  

+

   return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +

            (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);

 }

@@ -236,7 +236,7 @@ WriteLocalApicReg (
 /**

   Send an IPI by writing to ICR.

 

-  This function returns after the IPI has been accepted by the target processor. 

+  This function returns after the IPI has been accepted by the target processor.

 

   @param  IcrLow 32-bit value to be written to the low half of ICR.

   @param  ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.

@@ -301,7 +301,7 @@ SendIpi (
 

   } else {

     //

-    // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an 

+    // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an

     // interrupt in x2APIC mode.

     //

     MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow;

@@ -414,7 +414,7 @@ SetApicMode (
   Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.

 

   In xAPIC mode, the initial local APIC ID may be different from current APIC ID.

-  In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, 

+  In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,

   the 32-bit local APIC ID is returned as initial APIC ID.

 

   @return  32-bit initial local APIC ID of the executing processor.

@@ -435,7 +435,7 @@ GetInitialApicId (
     //

     AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);

     //

-    // If CPUID Leaf B is supported, 

+    // If CPUID Leaf B is supported,

     // And CPUID.0BH:EBX[15:0] reports a non-zero value,

     // Then the initial 32-bit APIC ID = CPUID.0BH:EDX

     // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]

@@ -492,7 +492,7 @@ GetApicVersion (
 /**

   Send a Fixed IPI to a specified target processor.

 

-  This function returns after the IPI has been accepted by the target processor. 

+  This function returns after the IPI has been accepted by the target processor.

 

   @param  ApicId   The local APIC ID of the target processor.

   @param  Vector   The vector number of the interrupt being sent.

@@ -516,7 +516,7 @@ SendFixedIpi (
 /**

   Send a Fixed IPI to all processors excluding self.

 

-  This function returns after the IPI has been accepted by the target processors. 

+  This function returns after the IPI has been accepted by the target processors.

 

   @param  Vector   The vector number of the interrupt being sent.

 **/

@@ -539,7 +539,7 @@ SendFixedIpiAllExcludingSelf (
 /**

   Send a SMI IPI to a specified target processor.

 

-  This function returns after the IPI has been accepted by the target processor. 

+  This function returns after the IPI has been accepted by the target processor.

 

   @param  ApicId   Specify the local APIC ID of the target processor.

 **/

@@ -560,7 +560,7 @@ SendSmiIpi (
 /**

   Send a SMI IPI to all processors excluding self.

 

-  This function returns after the IPI has been accepted by the target processors. 

+  This function returns after the IPI has been accepted by the target processors.

 **/

 VOID

 EFIAPI

@@ -580,7 +580,7 @@ SendSmiIpiAllExcludingSelf (
 /**

   Send an INIT IPI to a specified target processor.

 

-  This function returns after the IPI has been accepted by the target processor. 

+  This function returns after the IPI has been accepted by the target processor.

 

   @param  ApicId   Specify the local APIC ID of the target processor.

 **/

@@ -601,7 +601,7 @@ SendInitIpi (
 /**

   Send an INIT IPI to all processors excluding self.

 

-  This function returns after the IPI has been accepted by the target processors. 

+  This function returns after the IPI has been accepted by the target processors.

 **/

 VOID

 EFIAPI

@@ -621,7 +621,7 @@ SendInitIpiAllExcludingSelf (
 /**

   Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.

 

-  This function returns after the IPI has been accepted by the target processor. 

+  This function returns after the IPI has been accepted by the target processor.

 

   if StartupRoutine >= 1M, then ASSERT.

   if StartupRoutine is not multiple of 4K, then ASSERT.

@@ -658,7 +658,7 @@ SendInitSipiSipi (
 /**

   Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.

 

-  This function returns after the IPI has been accepted by the target processors. 

+  This function returns after the IPI has been accepted by the target processors.

 

   if StartupRoutine >= 1M, then ASSERT.

   if StartupRoutine is not multiple of 4K, then ASSERT.

@@ -862,7 +862,7 @@ InitializeApicTimer (
     Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);

     Dcr.Bits.DivideValue1 = (Divisor & 0x3);

     Dcr.Bits.DivideValue2 = (Divisor >> 2);

-    WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32); 

+    WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);

   }

 

   //

@@ -992,13 +992,13 @@ SendApicEoi (
 }

 

 /**

-  Get the 32-bit address that a device should use to send a Message Signaled 

+  Get the 32-bit address that a device should use to send a Message Signaled

   Interrupt (MSI) to the Local APIC of the currently executing processor.

 

   @return 32-bit address used to send an MSI to the Local APIC.

 **/

 UINT32

-EFIAPI    

+EFIAPI

 GetApicMsiAddress (

   VOID

   )

@@ -1006,7 +1006,7 @@ GetApicMsiAddress (
   LOCAL_APIC_MSI_ADDRESS  MsiAddress;

 

   //

-  // Return address for an MSI interrupt to be delivered only to the APIC ID 

+  // Return address for an MSI interrupt to be delivered only to the APIC ID

   // of the currently executing processor.

   //

   MsiAddress.Uint32             = 0;

@@ -1014,17 +1014,17 @@ GetApicMsiAddress (
   MsiAddress.Bits.DestinationId = GetApicId ();

   return MsiAddress.Uint32;

 }

-    

+

 /**

-  Get the 64-bit data value that a device should use to send a Message Signaled 

+  Get the 64-bit data value that a device should use to send a Message Signaled

   Interrupt (MSI) to the Local APIC of the currently executing processor.

 

   If Vector is not in range 0x10..0xFE, then ASSERT().

   If DeliveryMode is not supported, then ASSERT().

-  

-  @param  Vector          The 8-bit interrupt vector associated with the MSI.  

+

+  @param  Vector          The 8-bit interrupt vector associated with the MSI.

                           Must be in the range 0x10..0xFE

-  @param  DeliveryMode    A 3-bit value that specifies how the recept of the MSI 

+  @param  DeliveryMode    A 3-bit value that specifies how the recept of the MSI

                           is handled.  The only supported values are:

                             0: LOCAL_APIC_DELIVERY_MODE_FIXED

                             1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY

@@ -1032,19 +1032,19 @@ GetApicMsiAddress (
                             4: LOCAL_APIC_DELIVERY_MODE_NMI

                             5: LOCAL_APIC_DELIVERY_MODE_INIT

                             7: LOCAL_APIC_DELIVERY_MODE_EXTINT

-                          

-  @param  LevelTriggered  TRUE specifies a level triggered interrupt.  

+

+  @param  LevelTriggered  TRUE specifies a level triggered interrupt.

                           FALSE specifies an edge triggered interrupt.

   @param  AssertionLevel  Ignored if LevelTriggered is FALSE.

-                          TRUE specifies a level triggered interrupt that active 

+                          TRUE specifies a level triggered interrupt that active

                           when the interrupt line is asserted.

-                          FALSE specifies a level triggered interrupt that active 

+                          FALSE specifies a level triggered interrupt that active

                           when the interrupt line is deasserted.

 

   @return 64-bit data value used to send an MSI to the Local APIC.

 **/

 UINT64

-EFIAPI    

+EFIAPI

 GetApicMsiValue (

   IN UINT8    Vector,

   IN UINTN    DeliveryMode,

@@ -1056,7 +1056,7 @@ GetApicMsiValue (
 

   ASSERT (Vector >= 0x10 && Vector <= 0xFE);

   ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);

-  

+

   MsiData.Uint64            = 0;

   MsiData.Bits.Vector       = Vector;

   MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;

diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
index 53e186858f..533607c19f 100644
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
@@ -4,15 +4,15 @@
 #  Note: Local APIC library assumes local APIC is enabled. It does not handle cases

 #  where local APIC is disabled.

 #

-#  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>

+#  Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>

 #  This program and the accompanying materials

 #  are licensed and made available under the terms and conditions of the BSD License

 #  which accompanies this distribution.  The full text of the license may be found at

 #  http://opensource.org/licenses/bsd-license.php

-#  

+#

 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-#  

+#

 ##

 

 [Defines]

@@ -22,7 +22,7 @@
   FILE_GUID                      = 967B6E05-F10D-4c10-8BF7-365291CA143F

   MODULE_TYPE                    = BASE

   VERSION_STRING                 = 1.1

-  LIBRARY_CLASS                  = LocalApicLib 

+  LIBRARY_CLASS                  = LocalApicLib

 

 #

 # The following information is for reference only and not required by the build tools.

diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.uni b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.uni
index 97f62273ba..70d95d4b06 100644
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.uni
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.uni
@@ -4,13 +4,13 @@
 // Note: Local APIC library assumes local APIC is enabled. It does not handle cases

 // where local APIC is disabled.

 //

-// Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>

+// Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>

 //

 // This program and the accompanying materials

 // are licensed and made available under the terms and conditions of the BSD License

 // which accompanies this distribution.  The full text of the license may be found at

 // http://opensource.org/licenses/bsd-license.php

-// 

+//

 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

 //