diff options
| author | Dong, Eric <eric.dong@intel.com> | 2019-08-16 11:57:30 +0800 |
|---|---|---|
| committer | Ray Ni <ray.ni@intel.com> | 2019-08-21 02:44:50 +0800 |
| commit | 9c90d39b600bd33c7e0600865e6d860d46ce95f3 (patch) | |
| tree | 0bfa402b2d8ca9ee91e7a90b4f01f1b66ff18012 /UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c | |
| parent | 95cfe6c24714a11c894070a0bf2f2ba08f0ff68b (diff) | |
| download | edk2-9c90d39b600bd33c7e0600865e6d860d46ce95f3.tar.gz edk2-9c90d39b600bd33c7e0600865e6d860d46ce95f3.tar.bz2 edk2-9c90d39b600bd33c7e0600865e6d860d46ce95f3.zip | |
UefiCpuPkg/CpuCommonFeaturesLib: Use new macros.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040
Below code is current implementation:
if (MsrRegister[ProcessorNumber].Bits.Lock == 0) {
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
MSR_IA32_FEATURE_CONTROL,
MSR_IA32_FEATURE_CONTROL_REGISTER,
Bits.Lock,
1
);
}
1. In first normal boot, the Bits.Lock is 0, 1 will be added
into the register table and then will set to the MSR.
2. Trig warm reboot, MSR value preserves. After normal boot phase,
the Bits.Lock is 1, so it will not be added into the register
table during the warm reboot phase.
3. Trig S3 then resume, the Bits.Lock change to 0 and Bits.Lock is
not added in register table, so it's still 0 after resume. This
is not an expect behavior. The expect value is the value should
always 1 after booting or resuming from S3.
The root cause for this issue is
1. driver bases on current value to insert the "set value action" to
the register table.
2. Some MSRs may reserve their value during warm reboot.
The solution for this issue is using new added macros for the MSRs which
preserve value during warm reboot.
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Diffstat (limited to 'UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c')
| -rw-r--r-- | UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c index fd43b8d662..238632f88a 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c @@ -2,7 +2,7 @@ This library registers CPU features defined in Intel(R) 64 and IA-32
Architectures Software Developer's Manual.
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -91,7 +91,7 @@ CpuCommonFeaturesLibConstructor ( if (IsCpuFeatureSupported (CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER)) {
Status = RegisterCpuFeature (
"Lock Feature Control Register",
- FeatureControlGetConfigData,
+ NULL,
LockFeatureControlRegisterSupport,
LockFeatureControlRegisterInitialize,
CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER,
@@ -102,7 +102,7 @@ CpuCommonFeaturesLibConstructor ( if (IsCpuFeatureSupported (CPU_FEATURE_SMX)) {
Status = RegisterCpuFeature (
"SMX",
- FeatureControlGetConfigData,
+ NULL,
SmxSupport,
SmxInitialize,
CPU_FEATURE_SMX,
@@ -114,7 +114,7 @@ CpuCommonFeaturesLibConstructor ( if (IsCpuFeatureSupported (CPU_FEATURE_VMX)) {
Status = RegisterCpuFeature (
"VMX",
- FeatureControlGetConfigData,
+ NULL,
VmxSupport,
VmxInitialize,
CPU_FEATURE_VMX,
@@ -214,7 +214,7 @@ CpuCommonFeaturesLibConstructor ( if (IsCpuFeatureSupported (CPU_FEATURE_LMCE)) {
Status = RegisterCpuFeature (
"LMCE",
- FeatureControlGetConfigData,
+ NULL,
LmceSupport,
LmceInitialize,
CPU_FEATURE_LMCE,
|