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authorStar Zeng <star.zeng@intel.com>2019-05-25 15:05:47 +0800
committerStar Zeng <star.zeng@intel.com>2019-06-06 18:51:44 +0800
commit484dc05005ea80280e184b20a6b8a08636276777 (patch)
treee1d8a7d0ba2e0fbb288b95c979a384a13d3bc73a /UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
parent3147da26350fbdffb851f00137a8d719adc31327 (diff)
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UefiCpuPkg CpuCommFeaturesLib: Disable TraceEn at the beginning
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1809 Current code disables TraceEn at the end of ProcTraceInitialize(), then there will be much memory allocated even when ProcTrace feature is disabled. This patch updates code to disable TraceEn and return at the beginning of ProcTraceInitialize() when when ProcTrace feature is disabled. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Kevin Li <kevin.y.li@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
Diffstat (limited to 'UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c')
-rw-r--r--UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c42
1 files changed, 21 insertions, 21 deletions
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
index da6f6beb94..b98eb116b7 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
@@ -199,22 +199,6 @@ ProcTraceInitialize (
ProcTraceData = (PROC_TRACE_DATA *) ConfigData;
ASSERT (ProcTraceData != NULL);
- MemRegionBaseAddr = 0;
- FirstIn = FALSE;
-
- if (ProcTraceData->ThreadMemRegionTable == NULL) {
- FirstIn = TRUE;
- DEBUG ((DEBUG_INFO, "Initialize Processor Trace\n"));
- }
-
- ///
- /// Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding
- ///
- MemRegionSize = (UINT32) (1 << (ProcTraceData->ProcTraceMemSize + 12));
- if (FirstIn) {
- DEBUG ((DEBUG_INFO, "ProcTrace: MemSize requested: 0x%X \n", MemRegionSize));
- }
-
//
// Clear MSR_IA32_RTIT_CTL[0] and IA32_RTIT_STS only if MSR_IA32_RTIT_CTL[0]==1b
//
@@ -243,6 +227,26 @@ ProcTraceInitialize (
);
}
+ if (!State) {
+ return RETURN_SUCCESS;
+ }
+
+ MemRegionBaseAddr = 0;
+ FirstIn = FALSE;
+
+ if (ProcTraceData->ThreadMemRegionTable == NULL) {
+ FirstIn = TRUE;
+ DEBUG ((DEBUG_INFO, "Initialize Processor Trace\n"));
+ }
+
+ ///
+ /// Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding
+ ///
+ MemRegionSize = (UINT32) (1 << (ProcTraceData->ProcTraceMemSize + 12));
+ if (FirstIn) {
+ DEBUG ((DEBUG_INFO, "ProcTrace: MemSize requested: 0x%X \n", MemRegionSize));
+ }
+
if (FirstIn) {
//
// Let BSP allocate and create the necessary memory region (Aligned to the size of
@@ -459,11 +463,7 @@ ProcTraceInitialize (
CtrlReg.Bits.OS = 1;
CtrlReg.Bits.User = 1;
CtrlReg.Bits.BranchEn = 1;
- if (!State) {
- CtrlReg.Bits.TraceEn = 0;
- } else {
- CtrlReg.Bits.TraceEn = 1;
- }
+ CtrlReg.Bits.TraceEn = 1;
CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber,
Msr,