UefiCpuPkg/CpuCommonFeaturesLib: Aesni.c uses BIT0 and BIT1 reversedly

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1621

According to Intel SDM as below, the BIT0 should be treated as
lock bit, and BIT1 should be treated as disable(1)/enable(0) bit.

"11b: AES instructions are not available until next
RESET.
Otherwise, AES instructions are available.
If the configuration is not 01b, AES
instructions can be mis-configured if a privileged agent
unintentionally writes 11b"

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Chandana Kumar <chandana.c.kumar@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
index 56b1b551d9..3f7c933e51 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
@@ -1,7 +1,7 @@
 /** @file

   AESNI feature.

 

-  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -123,7 +123,7 @@ AesniInitialize (
         MSR_SANDY_BRIDGE_FEATURE_CONFIG,

         MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER,

         Bits.AESConfiguration,

-        BIT1 | ((State) ? 0 : BIT0)

+        BIT0 | ((State) ? 0 : BIT1)

         );

     }

   }