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| author | Ruiyu Ni <ruiyu.ni@intel.com> | 2018-05-25 16:29:48 +0800 |
|---|---|---|
| committer | Ruiyu Ni <ruiyu.ni@intel.com> | 2018-05-28 14:49:29 +0800 |
| commit | 36dd3c781e204a97d548ce3595ef6f6b6337bc1f (patch) | |
| tree | 8d1fa93bf276f4eee8091df427134fba3b9d6680 /UefiCpuPkg/Library/CpuCommonFeaturesLib | |
| parent | 5a57246eab80f00ae2481970d12a2abc345a2730 (diff) | |
| download | edk2-36dd3c781e204a97d548ce3595ef6f6b6337bc1f.tar.gz edk2-36dd3c781e204a97d548ce3595ef6f6b6337bc1f.tar.bz2 edk2-36dd3c781e204a97d548ce3595ef6f6b6337bc1f.zip | |
PcAtChipsetPkg/PcRtc: Add two new PCD for RTC Index/Target registers
In certain HW implementation, the BIT7 of RTC Index register(0x70) is
for NMI sources enable/disable but the BIT7 of 0x70 cannot be read
before writing. Software which doesn't want to change the NMI sources
enable/disable setting can write to the alias register 0x74, through
which only BIT0 ~ BIT6 of 0x70 is modified.
So two new PCDs are added so that platform can have the flexibility
to change the default RTC register addresses from 0x70/0x71 to
0x74/0x75.
With the new PCDs added, it can also support special HW that provides
RTC storage in a different register pairs.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Diffstat (limited to 'UefiCpuPkg/Library/CpuCommonFeaturesLib')
0 files changed, 0 insertions, 0 deletions