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| author | Ruiyu Ni <ruiyu.ni@intel.com> | 2018-02-08 14:43:20 +0800 |
|---|---|---|
| committer | Ruiyu Ni <ruiyu.ni@intel.com> | 2018-02-09 12:33:55 +0800 |
| commit | dc7363f848158564d8404c415061acf8c51ceb45 (patch) | |
| tree | 3a5064ff10db39f9d7f2d1e47ebde3fe5bb8d3aa /UefiCpuPkg/Library/CpuCommonFeaturesLib | |
| parent | 7506fe43a10d5f8148417812d204498995d9f1e7 (diff) | |
| download | edk2-dc7363f848158564d8404c415061acf8c51ceb45.tar.gz edk2-dc7363f848158564d8404c415061acf8c51ceb45.tar.bz2 edk2-dc7363f848158564d8404c415061acf8c51ceb45.zip | |
UefiCpuPkg/FeaturesLib: don't init MCi_CTL/STATUS when MCA's disabled
Today's McaInitialize() doesn't check State value before initialize
MCi_CTL and MCi_STATUS.
The patch fixes this issue by only initializing the two kinds of
MSRs when State is enabled.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Diffstat (limited to 'UefiCpuPkg/Library/CpuCommonFeaturesLib')
| -rw-r--r-- | UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c | 32 |
1 files changed, 17 insertions, 15 deletions
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c index 58dc45aeda..cc64dbbf0a 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c @@ -1,7 +1,7 @@ /** @file
Machine Check features.
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -140,25 +140,27 @@ McaInitialize ( MSR_IA32_MCG_CAP_REGISTER McgCap;
UINT32 BankIndex;
- McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
- for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) {
- CPU_REGISTER_TABLE_WRITE64 (
- ProcessorNumber,
- Msr,
- MSR_IA32_MC0_CTL + BankIndex * 4,
- MAX_UINT64
- );
- }
-
- if (PcdGetBool (PcdIsPowerOnReset)) {
- for (BankIndex = 0; BankIndex < (UINTN) McgCap.Bits.Count; BankIndex++) {
+ if (State == TRUE) {
+ McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
+ for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) {
CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber,
Msr,
- MSR_IA32_MC0_STATUS + BankIndex * 4,
- 0
+ MSR_IA32_MC0_CTL + BankIndex * 4,
+ MAX_UINT64
);
}
+
+ if (PcdGetBool (PcdIsPowerOnReset)) {
+ for (BankIndex = 0; BankIndex < (UINTN) McgCap.Bits.Count; BankIndex++) {
+ CPU_REGISTER_TABLE_WRITE64 (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_MC0_STATUS + BankIndex * 4,
+ 0
+ );
+ }
+ }
}
return RETURN_SUCCESS;
|