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| author | Kuo, Ted <ted.kuo@intel.com> | 2022-12-16 20:46:26 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-12-19 06:12:56 +0000 |
| commit | 6acf72901a2e811a2838cafd496239a34779066a (patch) | |
| tree | 2e7fe55520ec9db7cea1189f9c98f25d82000a69 /UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | |
| parent | 4dd7b865565aea4d28bea1b8d57d62620f6015a9 (diff) | |
| download | edk2-6acf72901a2e811a2838cafd496239a34779066a.tar.gz edk2-6acf72901a2e811a2838cafd496239a34779066a.tar.bz2 edk2-6acf72901a2e811a2838cafd496239a34779066a.zip | |
UefiCpuPkg: Supporting S3 in 64bit PEI
https://bugzilla.tianocore.org/show_bug.cgi?id=4195
1.Updated the GDT table in VTF0 to align with the one in S3Resume2Pei.
By doing so can simplify the changes to enable S3 in 64bit PEI.
2.Use SwitchStack() between PEI and SMM in S3 resume path when both
are in the same execution mode.
3.Transfer from PEI to OS waking vector by calling SwitchStack() when
both are in the same execution mode.
4.Removed the debug assertion in S3Resume.c to support 64bit PEI.
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Cc: Chinni B Duggapu <chinni.b.duggapu@intel.com>
Signed-off-by: Ted Kuo <ted.kuo@intel.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c')
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c index 9b45c442c9..fb4a44eab6 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -1,7 +1,7 @@ /** @file
Code for Processor S3 restoration
-Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -783,7 +783,11 @@ SmmRestoreCpu ( SmmS3ResumeState = mSmmS3ResumeState;
ASSERT (SmmS3ResumeState != NULL);
- if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {
+ //
+ // Setup 64bit IDT in 64bit SMM env when called from 32bit PEI.
+ // Note: 64bit PEI and 32bit DXE is not a supported combination.
+ //
+ if ((SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) && (FeaturePcdGet (PcdDxeIplSwitchToLongMode) == TRUE)) {
//
// Save the IA32 IDT Descriptor
//
@@ -846,9 +850,10 @@ SmmRestoreCpu ( DEBUG ((DEBUG_INFO, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState->ReturnStackPointer));
//
- // If SMM is in 32-bit mode, then use SwitchStack() to resume PEI Phase
+ // If SMM is in 32-bit mode or PcdDxeIplSwitchToLongMode is FALSE, then use SwitchStack() to resume PEI Phase.
+ // Note: 64bit PEI and 32bit DXE is not a supported combination.
//
- if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_32) {
+ if ((SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_32) || (FeaturePcdGet (PcdDxeIplSwitchToLongMode) == FALSE)) {
DEBUG ((DEBUG_INFO, "Call SwitchStack() to return to S3 Resume in PEI Phase\n"));
SwitchStack (
|