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| author | Leo Duran <leo.duran@amd.com> | 2017-02-27 01:43:07 +0800 |
|---|---|---|
| committer | Star Zeng <star.zeng@intel.com> | 2017-03-01 12:53:03 +0800 |
| commit | 241f914975d50e34f6da57d1e5ac60eedb5d52de (patch) | |
| tree | 1d619fc53b2170008dd92f7eef0ddbf8ffe071a7 /UefiCpuPkg/PiSmmCpuDxeSmm/Ia32 | |
| parent | ab1a5a58c95937998f3ecf384a8940130511e234 (diff) | |
| download | edk2-241f914975d50e34f6da57d1e5ac60eedb5d52de.tar.gz edk2-241f914975d50e34f6da57d1e5ac60eedb5d52de.tar.bz2 edk2-241f914975d50e34f6da57d1e5ac60eedb5d52de.zip | |
UefiCpuPkg/PiSmmCpuDxeSmm: Add support for PCD PcdPteMemoryEncryptionAddressOrMask
This PCD holds the address mask for page table entries when memory
encryption is enabled on AMD processors supporting the Secure Encrypted
Virtualization (SEV) feature.
The mask is applied when page tables entriees are created or modified.
CC: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/Ia32')
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c index c1f4b7e13d..119810abc7 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c @@ -2,6 +2,8 @@ Page table manipulation functions for IA-32 processors
Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -204,7 +206,7 @@ SetPageTableAttributes ( PageTableSplitted = (PageTableSplitted || IsSplitted);
for (Index3 = 0; Index3 < 4; Index3++) {
- L2PageTable = (UINT64 *)(UINTN)(L3PageTable[Index3] & PAGING_4K_ADDRESS_MASK_64);
+ L2PageTable = (UINT64 *)(UINTN)(L3PageTable[Index3] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
if (L2PageTable == NULL) {
continue;
}
@@ -217,7 +219,7 @@ SetPageTableAttributes ( // 2M
continue;
}
- L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & PAGING_4K_ADDRESS_MASK_64);
+ L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
if (L1PageTable == NULL) {
continue;
}
|