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| author | Yao, Jiewen <jiewen.yao@intel.com> | 2015-11-26 07:01:08 +0000 |
|---|---|---|
| committer | jyao1 <jyao1@Edk2> | 2015-11-26 07:01:08 +0000 |
| commit | 8e496a7abcb78c36b0af47ed473096ef7f171606 (patch) | |
| tree | 780d46ef05f34a2c82220006b79cfdc8e7f70fee /UefiCpuPkg/PiSmmCpuDxeSmm/Ia32 | |
| parent | 989edf1633ab9a9fc9904c90b1a49ae84c5bbbe2 (diff) | |
| download | edk2-8e496a7abcb78c36b0af47ed473096ef7f171606.tar.gz edk2-8e496a7abcb78c36b0af47ed473096ef7f171606.tar.bz2 edk2-8e496a7abcb78c36b0af47ed473096ef7f171606.zip | |
Always set WP in CR0.
Always set RW+P bit for page table by default.
So that we can use write-protection for code later.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18960 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/Ia32')
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 2 | ||||
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S index fbaa0725f0..ec5b9a0b04 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S @@ -123,7 +123,7 @@ L11: L12: # as cr4.PGE is not set here, refresh cr3
movl %eax, %cr4 # in PreModifyMtrrs() to flush TLB.
movl %cr0, %ebx
- orl $0x080000000, %ebx # enable paging
+ orl $0x080010000, %ebx # enable paging + WP
movl %ebx, %cr0
leal DSC_OFFSET(%edi),%ebx
movw DSC_DS(%ebx),%ax
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm index 8a12927300..ac1a9b48dd 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm @@ -129,7 +129,7 @@ gSmiCr3 DD ? @@: ; as cr4.PGE is not set here, refresh cr3
mov cr4, eax ; in PreModifyMtrrs() to flush TLB.
mov ebx, cr0
- or ebx, 080000000h ; enable paging
+ or ebx, 080010000h ; enable paging + WP
mov cr0, ebx
lea ebx, [edi + DSC_OFFSET]
mov ax, [ebx + DSC_DS]
|