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| author | Laszlo Ersek <lersek@redhat.com> | 2018-03-23 20:54:19 +0100 |
|---|---|---|
| committer | Laszlo Ersek <lersek@redhat.com> | 2018-04-04 16:44:27 +0200 |
| commit | d22c995a481485d8240453a9e5ea9af1d87a4c80 (patch) | |
| tree | 857138108b4b3d2d3123591c1de010d6631ab198 /UefiCpuPkg/PiSmmCpuDxeSmm/Ia32 | |
| parent | 9686a4678de78e797e1368b9ff131890d3dee41b (diff) | |
| download | edk2-d22c995a481485d8240453a9e5ea9af1d87a4c80.tar.gz edk2-d22c995a481485d8240453a9e5ea9af1d87a4c80.tar.bz2 edk2-d22c995a481485d8240453a9e5ea9af1d87a4c80.zip | |
UefiCpuPkg/PiSmmCpuDxeSmm: use mnemonics for FXSAVE(64)/FXRSTOR(64)
NASM introduced FXSAVE / FXRSTOR support in commit 900fa5b26b8f ("NASM
0.98p3-hpa", 2002-04-30), which commit stands for the nasm-0.98p3-hpa
release.
NASM introduced FXSAVE64 / FXRSTOR64 support in commit 3a014348ca15
("insns: add FXSAVE64/FXRSTOR64, drop np prefix", 2010-07-07), which was
part of the "nasm-2.09" release.
Edk2 requires nasm-2.10 or later for use with the GCC toolchain family,
and nasm-2.12.01 or later for use with all other toolchain families.
Replace the binary encoding of the FXSAVE(64)/FXRSTOR(64) instructions
with mnemonics.
I verified that the "Ia32/SmiException.obj", "X64/SmiEntry.obj" and
"X64/SmiException.obj" files are rebuilt after this patch, without any
change in content.
This patch removes the last instructions encoded with DBs from
PiSmmCpuDxeSmm.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/Ia32')
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm index 7c80a6ae91..fa02c1016c 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm @@ -382,7 +382,7 @@ ASM_PFX(PageFaultIdtHandlerSmmProfile): ;; FX_SAVE_STATE_IA32 FxSaveState;
sub esp, 512
mov edi, esp
- db 0xf, 0xae, 0x7 ;fxsave [edi]
+ fxsave [edi]
; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
cld
@@ -410,7 +410,7 @@ ASM_PFX(PageFaultIdtHandlerSmmProfile): ;; FX_SAVE_STATE_IA32 FxSaveState;
mov esi, esp
- db 0xf, 0xae, 0xe ; fxrstor [esi]
+ fxrstor [esi]
add esp, 512
;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
@@ -582,7 +582,7 @@ PFHandlerEntry: clts
sub esp, 512
mov edi, esp
- db 0xf, 0xae, 0x7 ;fxsave [edi]
+ fxsave [edi]
; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
cld
@@ -612,7 +612,7 @@ PFHandlerEntry: ;; FX_SAVE_STATE_IA32 FxSaveState;
mov esi, esp
- db 0xf, 0xae, 0xe ; fxrstor [esi]
+ fxrstor [esi]
add esp, 512
;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|