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| author | Michael Kinney <michael.d.kinney@intel.com> | 2015-12-24 00:13:54 +0000 |
|---|---|---|
| committer | mdkinney <mdkinney@Edk2> | 2015-12-24 00:13:54 +0000 |
| commit | e9b3a6c926a65f568c1a736dfc6e9957cc7cf3de (patch) | |
| tree | 955a65ce175128ae456f25c05f2549117e947887 /UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | |
| parent | 3eed6dda20149609ceb8b50318a780f1a1422341 (diff) | |
| download | edk2-e9b3a6c926a65f568c1a736dfc6e9957cc7cf3de.tar.gz edk2-e9b3a6c926a65f568c1a736dfc6e9957cc7cf3de.tar.bz2 edk2-e9b3a6c926a65f568c1a736dfc6e9957cc7cf3de.zip | |
UefiCpuPkg/PiSmmCpuDxeSmm: Correct CPUID leaf used to detect SMM mode
Use Bit 29 of CPUID leaf CPUID_EXTENDED_CPU_SIG (0x80000001) to
determine the SMM save state mode. The previous version of this
code used CPUID leaf CPUID_VERSION_INFO (0x00000001).
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19503 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c')
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c index fb4655128f..949dd4e5c1 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -913,13 +913,18 @@ PiCpuSmmEntry ( //
// Retrieve CPU Family
//
- AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);
+ AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL);
FamilyId = (RegEax >> 8) & 0xf;
ModelId = (RegEax >> 4) & 0xf;
if (FamilyId == 0x06 || FamilyId == 0x0f) {
ModelId = ModelId | ((RegEax >> 12) & 0xf0);
}
+ RegEdx = 0;
+ AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
+ if (RegEax >= CPUID_EXTENDED_CPU_SIG) {
+ AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);
+ }
//
// Determine the mode of the CPU at the time an SMI occurs
// Intel(R) 64 and IA-32 Architectures Software Developer's Manual
|