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| author | Jiaxin Wu <jiaxin.wu@intel.com> | 2024-05-31 14:35:27 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2024-06-14 07:02:37 +0000 |
| commit | af2bbe1b79251f46efaca2ed36860105272dd14f (patch) | |
| tree | 286172f8e617b4beb8c72e91742ad12d3fbbad4a /UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | |
| parent | 712797cf19acd292bf203522a79e40e7e13d268b (diff) | |
| download | edk2-af2bbe1b79251f46efaca2ed36860105272dd14f.tar.gz edk2-af2bbe1b79251f46efaca2ed36860105272dd14f.tar.bz2 edk2-af2bbe1b79251f46efaca2ed36860105272dd14f.zip | |
UefiCpuPkg: Add PcdCpuSmmApSyncTimeout2 PCD
Provide the capability for platform to specifies the 2nd
timeout value in microseconds for the BSP/AP in SMM to wait for
one another to enter SMM.
The added interface can enhance the flexibility of timeout
configuration. In some cases, certain processors may not be
able to enter SMI, and prolonged waiting could lead to
kernel soft/hard lockup. We have now defined two timeouts.
The first timeout can be set to a smaller value to reduce
the waiting period. Processors that are unable to enter SMI
will be woken up through SMIIPL to enter SMI, followed by
a second waiting period. The second timeout can be set to a
larger value to prevent delays in processors entering SMI
case due to the long instruction execution.
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf')
0 files changed, 0 insertions, 0 deletions