Revert "UefiCpuPkg/PiSmmCpu: Enable 5 level paging when CPU supports"

This reverts commit 7365eb2c8cf1d7112330d09918c0c67e8d0b827a.
Commit
7c5010c7f8 MdePkg/BaseLib.h: Update IA32_CR4 structure for 5-level paging
technically breaks the EDKII development process documented in
https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Development-Process
and Maintainers.txt in EDKII repo root directory.

The voilation is commit 7c5010c7f8 doesn't have a Reviewed-by or
Acked-by from MdePkg maintainers.

In order to revert 7c5010c7f8, 7365eb2c8 needs to revert first otherwise
simply reverting 7c5010c7f8 will cause build break.

Signed-off-by: Ray Ni <ray.ni@intel.com>

1 files changed, 0 insertions, 12 deletions

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index 271492a9d7..741e4b7da2 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -69,7 +69,6 @@ extern ASM_PFX(mXdSupported)
 global ASM_PFX(gPatchXdSupported)

 global ASM_PFX(gPatchSmiStack)

 global ASM_PFX(gPatchSmiCr3)

-global ASM_PFX(gPatch5LevelPagingSupport)

 global ASM_PFX(gcSmiHandlerTemplate)

 global ASM_PFX(gcSmiHandlerSize)

 

@@ -125,17 +124,6 @@ ProtFlatMode:
 ASM_PFX(gPatchSmiCr3):

     mov     cr3, rax

     mov     eax, 0x668                   ; as cr4.PGE is not set here, refresh cr3

-

-    mov     cl, strict byte 0            ; source operand will be patched

-ASM_PFX(gPatch5LevelPagingSupport):

-    cmp     cl, 0

-    je      SkipEnable5LevelPaging

-    ;

-    ; Enable 5-Level Paging bit

-    ;

-    bts     eax, 12                     ; Set LA57 bit (bit #12)

-SkipEnable5LevelPaging:

-

     mov     cr4, rax                    ; in PreModifyMtrrs() to flush TLB.

 ; Load TSS

     sub     esp, 8                      ; reserve room in stack