UefiCpuPkg/PiSmmCpu: Enable 5L paging only when phy addr line > 48

Today's behavior is to enable 5l paging when CPU supports it
(CPUID[7,0].ECX.BIT[16] is set).

The patch changes the behavior to enable 5l paging when two
conditions are both met:
1. CPU supports it;
2. The max physical address bits is bigger than 48.

Because 4-level paging can support to address physical address up to
2^48 - 1, there is no need to enable 5-level paging with max
physical address bits <= 48.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index 271492a9d7..db06d22d51 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -69,7 +69,7 @@ extern ASM_PFX(mXdSupported)
 global ASM_PFX(gPatchXdSupported)

 global ASM_PFX(gPatchSmiStack)

 global ASM_PFX(gPatchSmiCr3)

-global ASM_PFX(gPatch5LevelPagingSupport)

+global ASM_PFX(gPatch5LevelPagingNeeded)

 global ASM_PFX(gcSmiHandlerTemplate)

 global ASM_PFX(gcSmiHandlerSize)

 

@@ -127,7 +127,7 @@ ASM_PFX(gPatchSmiCr3):
     mov     eax, 0x668                   ; as cr4.PGE is not set here, refresh cr3

 

     mov     cl, strict byte 0            ; source operand will be patched

-ASM_PFX(gPatch5LevelPagingSupport):

+ASM_PFX(gPatch5LevelPagingNeeded):

     cmp     cl, 0

     je      SkipEnable5LevelPaging

     ;