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| author | Sheng Wei <w.sheng@intel.com> | 2023-11-09 16:21:06 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-12-07 09:43:43 +0000 |
| commit | 04d47a9bf0068b88453154e2028a26b626c04147 (patch) | |
| tree | 6e4b18dd2a8146bddd2df7d80d7c9503b47c268a /UefiCpuPkg/PiSmmCpuDxeSmm/X64 | |
| parent | b5f20eca8a08c2921b4844e736f97d3450144ed5 (diff) | |
| download | edk2-04d47a9bf0068b88453154e2028a26b626c04147.tar.gz edk2-04d47a9bf0068b88453154e2028a26b626c04147.tar.bz2 edk2-04d47a9bf0068b88453154e2028a26b626c04147.zip | |
UefiCpuPkg: Use macro CR4_CET_BIT to replace hard code value in Cet.nasm.
Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Wu Jiaxin <jiaxin.wu@intel.com>
Cc: Tan Dun <dun.tan@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/X64')
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm index 8bbdbb31cc..58a3c37097 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm @@ -1,10 +1,11 @@ ;------------------------------------------------------------------------------ ;
-; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2019 - 2023, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;-------------------------------------------------------------------------------
%include "Nasm.inc"
+%include "Cet.inc"
DEFAULT REL
SECTION .text
@@ -17,7 +18,7 @@ ASM_PFX(DisableCet): incsspq rax
mov rax, cr4
- btr eax, 23 ; clear CET
+ btr eax, CR4_CET_BIT ; clear CET
mov cr4, rax
ret
@@ -25,7 +26,7 @@ global ASM_PFX(EnableCet) ASM_PFX(EnableCet):
mov rax, cr4
- bts eax, 23 ; set CET
+ bts eax, CR4_CET_BIT ; set CET
mov cr4, rax
; use jmp to skip the check for ret
|