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| author | Jiewen Yao <jiewen.yao@intel.com> | 2018-11-03 19:59:01 +0800 |
|---|---|---|
| committer | Ruiyu Ni <ruiyu.ni@intel.com> | 2018-11-08 00:13:26 +0800 |
| commit | c60d36b4d1ee1f69b7cca897d3621dfa951895c2 (patch) | |
| tree | e17cc028459a56d3ae8506e284fffe28f35526b7 /UefiCpuPkg/PiSmmCpuDxeSmm/X64 | |
| parent | b66e38b50134728614bbca2a2449a36a5dc2bd91 (diff) | |
| download | edk2-c60d36b4d1ee1f69b7cca897d3621dfa951895c2.tar.gz edk2-c60d36b4d1ee1f69b7cca897d3621dfa951895c2.tar.bz2 edk2-c60d36b4d1ee1f69b7cca897d3621dfa951895c2.zip | |
UefiCpuPkg/SmmCpu: Block access-out only when static paging is used
When static paging is disabled, page table for below 4GB is created
and page table for above 4GB is created dynamically in page fault
handler.
Today's implementation only allow SMM access-out to below types of
memory address no matter static paging is enabled or not:
1. Reserved, run time and ACPI NVS type
2. MMIO
But certain platform feature like RAS may need to access other types
of memory from SMM. Today's code blocks these platforms.
This patch simplifies the policy to only block when static paging
is used so that the static paging can be disabled in these platforms
to meet their SMM access-out need.
Setting PcdCpuSmmStaticPageTable to FALSE can disable the static
paging.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/X64')
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c index 5bb7d57238..117502dafa 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -1,7 +1,7 @@ /** @file
Page Fault (#PF) handler for X64 processors
-Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
This program and the accompanying materials
@@ -890,7 +890,7 @@ SmiPFHandler ( CpuDeadLoop ();
}
- if (IsSmmCommBufferForbiddenAddress (PFAddress)) {
+ if (mCpuSmmStaticPageTable && IsSmmCommBufferForbiddenAddress (PFAddress)) {
DumpCpuContext (InterruptType, SystemContext);
DEBUG ((DEBUG_ERROR, "Access SMM communication forbidden address (0x%lx)!\n", PFAddress));
DEBUG_CODE (
|