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authorLaszlo Ersek <lersek@redhat.com>2018-03-23 20:54:19 +0100
committerLaszlo Ersek <lersek@redhat.com>2018-04-04 16:44:27 +0200
commitd22c995a481485d8240453a9e5ea9af1d87a4c80 (patch)
tree857138108b4b3d2d3123591c1de010d6631ab198 /UefiCpuPkg/PiSmmCpuDxeSmm/X64
parent9686a4678de78e797e1368b9ff131890d3dee41b (diff)
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UefiCpuPkg/PiSmmCpuDxeSmm: use mnemonics for FXSAVE(64)/FXRSTOR(64)
NASM introduced FXSAVE / FXRSTOR support in commit 900fa5b26b8f ("NASM 0.98p3-hpa", 2002-04-30), which commit stands for the nasm-0.98p3-hpa release. NASM introduced FXSAVE64 / FXRSTOR64 support in commit 3a014348ca15 ("insns: add FXSAVE64/FXRSTOR64, drop np prefix", 2010-07-07), which was part of the "nasm-2.09" release. Edk2 requires nasm-2.10 or later for use with the GCC toolchain family, and nasm-2.12.01 or later for use with all other toolchain families. Replace the binary encoding of the FXSAVE(64)/FXRSTOR(64) instructions with mnemonics. I verified that the "Ia32/SmiException.obj", "X64/SmiEntry.obj" and "X64/SmiException.obj" files are rebuilt after this patch, without any change in content. This patch removes the last instructions encoded with DBs from PiSmmCpuDxeSmm. Cc: Eric Dong <eric.dong@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/X64')
-rw-r--r--UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm6
-rw-r--r--UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm4
2 files changed, 4 insertions, 6 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index 5d731e2280..97c7b01d0d 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -182,8 +182,7 @@ _SmiHandler:
; Save FP registers
;
sub rsp, 0x200
- DB 0x48 ; FXSAVE64
- fxsave [rsp]
+ fxsave64 [rsp]
add rsp, -0x20
@@ -201,8 +200,7 @@ _SmiHandler:
;
; Restore FP registers
;
- DB 0x48 ; FXRSTOR64
- fxrstor [rsp]
+ fxrstor64 [rsp]
add rsp, 0x200
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm
index a8a9af3008..98c40949f5 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm
@@ -279,7 +279,7 @@ ASM_PFX(PageFaultIdtHandlerSmmProfile):
sub rsp, 512
mov rdi, rsp
- db 0xf, 0xae, 00000111y ;fxsave [rdi]
+ fxsave [rdi]
; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
cld
@@ -309,7 +309,7 @@ ASM_PFX(PageFaultIdtHandlerSmmProfile):
;; FX_SAVE_STATE_X64 FxSaveState;
mov rsi, rsp
- db 0xf, 0xae, 00001110y ; fxrstor [rsi]
+ fxrstor [rsi]
add rsp, 512
;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;