diff options
author | Liming Gao <liming.gao@intel.com> | 2018-06-27 21:14:20 +0800 |
---|---|---|
committer | Liming Gao <liming.gao@intel.com> | 2018-06-28 11:19:53 +0800 |
commit | 7367cc6c24d01b400d2370ffd58ae02854a56b32 (patch) | |
tree | c5b8a758492e188fb3246eb8a72f07340cd80d44 /UefiCpuPkg/PiSmmCpuDxeSmm | |
parent | 77695f4da3dc8eedb6fc7fc67f91ef6ccd22daee (diff) | |
download | edk2-7367cc6c24d01b400d2370ffd58ae02854a56b32.tar.gz edk2-7367cc6c24d01b400d2370ffd58ae02854a56b32.tar.bz2 edk2-7367cc6c24d01b400d2370ffd58ae02854a56b32.zip |
UefiCpuPkg: Clean up source files
1. Do not use tab characters
2. No trailing white space in one line
3. All files must end with CRLF
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm')
-rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c | 6 | ||||
-rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 10 | ||||
-rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 4 |
3 files changed, 10 insertions, 10 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c index 4c1499939b..4f1f67fe4a 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c @@ -1,6 +1,6 @@ /** @file
SMM CPU misc functions for Ia32 arch specific.
-
+
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -43,7 +43,7 @@ InitializeIDTSmmStackGuard ( /**
Initialize Gdt for all processors.
-
+
@param[in] Cr3 CR3 value.
@param[out] GdtStepSize The step size for GDT table.
@@ -80,7 +80,7 @@ InitGdt ( //
// IA32 Stack Guard need use task switch to switch stack that need
// write GDT and TSS, so AllocateCodePages() could not be used here
- // as code pages will be set to RO.
+ // as code pages will be set to RO.
//
GdtTssTables = (UINT8*)AllocatePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));
ASSERT (GdtTssTables != NULL);
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c index 17459c790c..9cf508a5c7 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -1,7 +1,7 @@ /** @file
SMM MP service implementation
-Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
This program and the accompanying materials
@@ -199,7 +199,7 @@ AllCpusInSmmWithExceptions ( /**
Has OS enabled Lmce in the MSR_IA32_MCG_EXT_CTL
-
+
@retval TRUE Os enable lmce.
@retval FALSE Os not enable lmce.
@@ -228,9 +228,9 @@ IsLmceOsEnabled ( }
/**
- Return if Local machine check exception signaled.
+ Return if Local machine check exception signaled.
- Indicates (when set) that a local machine check exception was generated. This indicates that the current machine-check event was
+ Indicates (when set) that a local machine check exception was generated. This indicates that the current machine-check event was
delivered to only the logical processor.
@retval TRUE LMCE was signaled.
@@ -1046,7 +1046,7 @@ CpuSmmDebugEntry ( )
{
SMRAM_SAVE_STATE_MAP *CpuSaveState;
-
+
if (FeaturePcdGet (PcdCpuSmmDebug)) {
ASSERT(CpuIndex < mMaxNumberOfCpus);
CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex];
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c index 6a5d453242..b7c3ad31e8 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c @@ -1,6 +1,6 @@ /** @file
SMM CPU misc functions for x64 arch specific.
-
+
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -40,7 +40,7 @@ InitializeIDTSmmStackGuard ( /**
Initialize Gdt for all processors.
-
+
@param[in] Cr3 CR3 value.
@param[out] GdtStepSize The step size for GDT table.
|