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| author | Sheng Wei <w.sheng@intel.com> | 2023-11-09 16:41:05 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-12-07 09:43:43 +0000 |
| commit | fd1dd8568c78c594540990eaa4fbe37fdd3b1839 (patch) | |
| tree | 2b68f0fe37895afcb29b9930b5d1e1b5273fc66e /UefiCpuPkg/PiSmmCpuDxeSmm | |
| parent | 3018685da8a46d1cfb5d7bdfcded16940709d9da (diff) | |
| download | edk2-fd1dd8568c78c594540990eaa4fbe37fdd3b1839.tar.gz edk2-fd1dd8568c78c594540990eaa4fbe37fdd3b1839.tar.bz2 edk2-fd1dd8568c78c594540990eaa4fbe37fdd3b1839.zip | |
UefiCpuPkg: Only change CR4.CET bit for enable and disable CET.
Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Wu Jiaxin <jiaxin.wu@intel.com>
Cc: Tan Dun <dun.tan@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm')
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 10 | ||||
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 10 |
2 files changed, 14 insertions, 6 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm index d17b1a7dd4..87a31b71a9 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -237,7 +237,9 @@ CetInterruptDone: bts ecx, 16 ; set WP
mov cr0, ecx
- mov eax, 0x668 | CR4_CET
+ ; set CR4.CET bit for enable CET
+ mov eax, cr4
+ bts eax, CR4_CET_BIT
mov cr4, eax
setssbsy
@@ -264,8 +266,10 @@ CetDone: cmp al, 0
jz CetDone2
- mov eax, 0x668
- mov cr4, eax ; disable CET
+ ; clear CR4.CET bit for disable CET
+ mov eax, cr4
+ btr eax, CR4_CET_BIT
+ mov cr4, eax
mov ecx, MSR_IA32_PL0_SSP
pop eax
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm index f72013a718..e7c51e6950 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -263,7 +263,9 @@ CetInterruptDone: bts ecx, 16 ; set WP
mov cr0, rcx
- mov eax, 0x668 | CR4_CET
+ ; set CR4.CET bit for enable CET
+ mov rax, cr4
+ bts rax, CR4_CET_BIT
mov cr4, rax
setssbsy
@@ -308,8 +310,10 @@ mCetSupportedAbsAddr: cmp al, 0
jz CetDone2
- mov eax, 0x668
- mov cr4, rax ; disable CET
+ ; clear CR4.CET bit for disable CET
+ mov rax, cr4
+ btr rax, CR4_CET_BIT
+ mov cr4, rax
mov ecx, MSR_IA32_INTERRUPT_SSP_TABLE_ADDR
pop rax
|