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| author | Kuo, Ted <ted.kuo@intel.com> | 2022-12-16 20:46:26 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-12-19 06:12:56 +0000 |
| commit | 6acf72901a2e811a2838cafd496239a34779066a (patch) | |
| tree | 2e7fe55520ec9db7cea1189f9c98f25d82000a69 /UefiCpuPkg/ResetVector | |
| parent | 4dd7b865565aea4d28bea1b8d57d62620f6015a9 (diff) | |
| download | edk2-6acf72901a2e811a2838cafd496239a34779066a.tar.gz edk2-6acf72901a2e811a2838cafd496239a34779066a.tar.bz2 edk2-6acf72901a2e811a2838cafd496239a34779066a.zip | |
UefiCpuPkg: Supporting S3 in 64bit PEI
https://bugzilla.tianocore.org/show_bug.cgi?id=4195
1.Updated the GDT table in VTF0 to align with the one in S3Resume2Pei.
By doing so can simplify the changes to enable S3 in 64bit PEI.
2.Use SwitchStack() between PEI and SMM in S3 resume path when both
are in the same execution mode.
3.Transfer from PEI to OS waking vector by calling SwitchStack() when
both are in the same execution mode.
4.Removed the debug assertion in S3Resume.c to support 64bit PEI.
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Cc: Chinni B Duggapu <chinni.b.duggapu@intel.com>
Signed-off-by: Ted Kuo <ted.kuo@intel.com>
Diffstat (limited to 'UefiCpuPkg/ResetVector')
| -rw-r--r-- | UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm | 63 |
1 files changed, 44 insertions, 19 deletions
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm index 0e79a3984b..f59fc6ead4 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm @@ -2,7 +2,7 @@ ; @file
; Transition from 16 bit real mode into 32 bit flat protected mode
;
-; Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2008 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;------------------------------------------------------------------------------
@@ -92,7 +92,7 @@ ALIGN 16 GDT_BASE:
; null descriptor
-NULL_SEL equ $-GDT_BASE
+NULL_SEL equ $-GDT_BASE ; Selector [0x0]
DW 0 ; limit 15:0
DW 0 ; base 15:0
DB 0 ; base 23:16
@@ -100,42 +100,67 @@ NULL_SEL equ $-GDT_BASE DB 0 ; limit 19:16, flags
DB 0 ; base 31:24
+; Spare segment descriptor
+SPARE1_SEL equ $-GDT_BASE ; Selector [0x8]
+ DW 0 ; limit 15:0
+ DW 0 ; base 15:0
+ DB 0 ; base 23:16
+ DB 0 ; sys flag, dpl, type
+ DB 0 ; limit 19:16, flags
+ DB 0 ; base 31:24
+
+; linear code segment descriptor
+LINEAR_CODE_SEL equ $-GDT_BASE ; Selector [0x10]
+ DW 0xffff ; limit 15:0
+ DW 0 ; base 15:0
+ DB 0 ; base 23:16
+ DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE32_TYPE) ; 09Bh
+ DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(1)|CODE64_FLAG(0)|UPPER_LIMIT(0xf) ; 0CFh
+ DB 0 ; base 31:24
+
; linear data segment descriptor
-LINEAR_SEL equ $-GDT_BASE
+LINEAR_SEL equ $-GDT_BASE ; Selector [0x18]
DW 0xffff ; limit 15:0
DW 0 ; base 15:0
DB 0 ; base 23:16
- DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(DATA32_TYPE)
- DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(1)|CODE64_FLAG(0)|UPPER_LIMIT(0xf)
+ DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(DATA32_TYPE) ; 093h
+ DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(1)|CODE64_FLAG(0)|UPPER_LIMIT(0xf) ; 0CFh
DB 0 ; base 31:24
-; linear code segment descriptor
-LINEAR_CODE_SEL equ $-GDT_BASE
+; Spare segment descriptor
+SPARE2_SEL equ $-GDT_BASE ; Selector [0x20]
+ DW 0 ; limit 15:0
+ DW 0 ; base 15:0
+ DB 0 ; base 23:16
+ DB 0 ; sys flag, dpl, type
+ DB 0 ; limit 19:16, flags
+ DB 0 ; base 31:24
+
+; linear code (16-bit) segment descriptor
+LINEAR_CODE16_SEL equ $-GDT_BASE ; Selector [0x28]
DW 0xffff ; limit 15:0
DW 0 ; base 15:0
DB 0 ; base 23:16
- DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE32_TYPE)
- DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(1)|CODE64_FLAG(0)|UPPER_LIMIT(0xf)
+ DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE32_TYPE) ; 09Bh
+ DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(0)|CODE64_FLAG(0)|UPPER_LIMIT(0xf) ; 08Fh
DB 0 ; base 31:24
-%ifdef ARCH_X64
-; linear code (64-bit) segment descriptor
-LINEAR_CODE64_SEL equ $-GDT_BASE
+; linear data (16-bit) segment descriptor
+LINEAR_DATA16_SEL equ $-GDT_BASE ; Selector [0x30]
DW 0xffff ; limit 15:0
DW 0 ; base 15:0
DB 0 ; base 23:16
- DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE64_TYPE)
- DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(0)|CODE64_FLAG(1)|UPPER_LIMIT(0xf)
+ DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(DATA32_TYPE) ; 093h
+ DB 0
DB 0 ; base 31:24
-%endif
-; linear code segment descriptor
-LINEAR_CODE16_SEL equ $-GDT_BASE
+; linear code (64-bit) segment descriptor
+LINEAR_CODE64_SEL equ $-GDT_BASE ; Selector [0x38]
DW 0xffff ; limit 15:0
DW 0 ; base 15:0
DB 0 ; base 23:16
- DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE32_TYPE)
- DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(0)|CODE64_FLAG(0)|UPPER_LIMIT(0xf)
+ DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE64_TYPE) ; 09Bh
+ DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(0)|CODE64_FLAG(1)|UPPER_LIMIT(0xf) ; 0AFh
DB 0 ; base 31:24
GDT_END:
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