diff options
| author | Eric Dong <eric.dong@intel.com> | 2018-10-15 08:30:37 +0800 |
|---|---|---|
| committer | Eric Dong <eric.dong@intel.com> | 2018-10-15 08:36:40 +0800 |
| commit | 55e8ff01af77117dc276b3481ae364141012c52b (patch) | |
| tree | 6c472d25261c0b83023412fefdcc8d654abd71e2 /UefiCpuPkg/Universal | |
| parent | 1ccc4d895dd8d659d016efcd6ef8a48749aba1d0 (diff) | |
| download | edk2-55e8ff01af77117dc276b3481ae364141012c52b.tar.gz edk2-55e8ff01af77117dc276b3481ae364141012c52b.tar.bz2 edk2-55e8ff01af77117dc276b3481ae364141012c52b.zip | |
UefiCpuPkg/S3Resume2Pei: disable paging before creating new page table.
V5:
1. Add ASSERT to indicate this assumption that environment is 32 bit mode.
2. Add description in INF about this driver's expected result
in different environment.
V4:
Only disable paging when it is enabled.
V3 changes:
No need to change inf file.
V2 changes:
Only disable paging in 32 bit mode, no matter it is enable or not.
V1 changes:
PEI Stack Guard needs to enable paging. This might cause #GP if code
trying to write CR3 register with PML4 page table while the processor
is enabled with PAE paging.
Simply disabling paging before updating CR3 can solve this conflict.
It's an regression caused by change: 0a0d5296e448fc350de1594c49b9c0deff7fad60
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1232
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Diffstat (limited to 'UefiCpuPkg/Universal')
| -rw-r--r-- | UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 17 | ||||
| -rw-r--r-- | UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf | 10 |
2 files changed, 27 insertions, 0 deletions
diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c index f164c1713b..05234a6312 100644 --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c @@ -964,6 +964,7 @@ S3RestoreConfig2 ( VOID *GuidHob;
BOOLEAN Build4GPageTableOnly;
BOOLEAN InterruptStatus;
+ IA32_CR0 Cr0;
TempAcpiS3Context = 0;
TempEfiBootScriptExecutorVariable = 0;
@@ -1045,6 +1046,13 @@ S3RestoreConfig2 ( //
GuidHob = GetFirstGuidHob (&gEfiAcpiVariableGuid);
if (GuidHob != NULL) {
+ //
+ // Below SwitchStack/AsmEnablePaging64 function has
+ // assumption that it's in 32 bits mode now.
+ // Add ASSERT code to indicate this assumption.
+ //
+ ASSERT(sizeof (UINTN) == sizeof (UINT32));
+
Status = PeiServicesLocatePpi (
&gPeiSmmAccessPpiGuid,
0,
@@ -1105,6 +1113,15 @@ S3RestoreConfig2 ( //
SetInterruptState (InterruptStatus);
+ Cr0.UintN = AsmReadCr0 ();
+ if (Cr0.Bits.PG != 0) {
+ //
+ // We're in 32-bit mode, with paging enabled. We can't set CR3 to
+ // the 64-bit page tables without first disabling paging.
+ //
+ Cr0.Bits.PG = 0;
+ AsmWriteCr0 (Cr0.UintN);
+ }
AsmWriteCr3 ((UINTN)SmmS3ResumeState->SmmS3Cr3);
//
diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf index 6ce1bf944c..4395daec5d 100644 --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf @@ -33,6 +33,16 @@ # VALID_ARCHITECTURES = IA32 X64
#
+#
+# This module is not always workable in IA32 and X64 mode. It has below result:
+# when it works with SMM mode:
+# ===============================
+# SMM:used SMM:unused
+# PEI:IA32 works works
+# PEI:X64 fails works
+# ===============================
+#
+
[Sources]
S3Resume.c
|