diff options
| author | Ruiyu Ni <ruiyu.ni@intel.com> | 2016-09-02 20:23:35 +0800 |
|---|---|---|
| committer | Ruiyu Ni <ruiyu.ni@intel.com> | 2017-03-31 13:57:33 +0800 |
| commit | 012f4054dbf0debbe913422d0fd3545b36cb5dc9 (patch) | |
| tree | e5e894ddb880684b0885c2518be2705dbc374c2f /UefiCpuPkg | |
| parent | b8f015999e01100065322fed662efa9584697e37 (diff) | |
| download | edk2-012f4054dbf0debbe913422d0fd3545b36cb5dc9.tar.gz edk2-012f4054dbf0debbe913422d0fd3545b36cb5dc9.tar.bz2 edk2-012f4054dbf0debbe913422d0fd3545b36cb5dc9.zip | |
UefiCpuPkg/MtrrLib: MtrrLibInitializeMtrrMask() uses definitions in CpuId.h
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Diffstat (limited to 'UefiCpuPkg')
| -rw-r--r-- | UefiCpuPkg/Library/MtrrLib/MtrrLib.c | 20 |
1 files changed, 9 insertions, 11 deletions
diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c index 2679725a17..415fc2ff41 100644 --- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c +++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c @@ -1054,22 +1054,20 @@ MtrrLibInitializeMtrrMask ( OUT UINT64 *MtrrValidAddressMask
)
{
- UINT32 RegEax;
- UINT8 PhysicalAddressBits;
+ UINT32 MaxExtendedFunction;
+ CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;
- AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
- if (RegEax >= 0x80000008) {
- AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
+ AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NULL);
- PhysicalAddressBits = (UINT8) RegEax;
-
- *MtrrValidBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;
- *MtrrValidAddressMask = *MtrrValidBitsMask & 0xfffffffffffff000ULL;
+ if (MaxExtendedFunction >= CPUID_VIR_PHY_ADDRESS_SIZE) {
+ AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL, NULL, NULL);
} else {
- *MtrrValidBitsMask = MTRR_LIB_MSR_VALID_MASK;
- *MtrrValidAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
+ VirPhyAddressSize.Bits.PhysicalAddressBits = 36;
}
+
+ *MtrrValidBitsMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;
+ *MtrrValidAddressMask = *MtrrValidBitsMask & 0xfffffffffffff000ULL;
}
|