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| author | Jiaxin Wu <jiaxin.wu@intel.com> | 2024-07-12 16:05:02 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2024-08-02 05:13:42 +0000 |
| commit | 9d8a5fbd0ca7ed563544e71d2dbdd23b0a3f53e3 (patch) | |
| tree | 859974f7ed958d311db97d1dddcec1720aa61d0d /UefiCpuPkg | |
| parent | bbee1cc852fa8676ed0b530b1c67c92f32f4f740 (diff) | |
| download | edk2-9d8a5fbd0ca7ed563544e71d2dbdd23b0a3f53e3.tar.gz edk2-9d8a5fbd0ca7ed563544e71d2dbdd23b0a3f53e3.tar.bz2 edk2-9d8a5fbd0ca7ed563544e71d2dbdd23b0a3f53e3.zip | |
UefiCpuPkg/PiSmmCpuDxeSmm: Enable single step after SmmProfile start
There is a bug in the existing code: the single step is always enabled
once the Page Fault (#PF) occurs, but it is only disabled when the SMM
Profile feature actually starts (see DebugExceptionHandler).
If the SMM Profile feature has not been started, this will result in
the single-step mode remaining enabled if a Page Fault occurs.
This patch is to enable the single-step debugging mode by setting the
Trap Flag only after SmmProfile feature starts.
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Diffstat (limited to 'UefiCpuPkg')
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 10 | ||||
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm | 6 |
2 files changed, 11 insertions, 5 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c index 5c0f9b4a3f..d54c4c180a 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c @@ -759,6 +759,11 @@ SmmProfileStart ( // The flag indicates SMM profile starts to work.
//
mSmmProfileStart = TRUE;
+
+ //
+ // Tell #PF handler to prepare a #DB subsequently.
+ //
+ mSetupDebugTrap = TRUE;
}
/**
@@ -1146,11 +1151,6 @@ InitSmmProfile ( // Initialize profile IDT.
//
InitIdtr ();
-
- //
- // Tell #PF handler to prepare a #DB subsequently.
- //
- mSetupDebugTrap = TRUE;
}
/**
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm index f329a988f8..cddc55fca5 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm @@ -13,6 +13,7 @@ ;-------------------------------------------------------------------------------
extern ASM_PFX(SmiPFHandler)
+extern ASM_PFX(mSetupDebugTrap)
global ASM_PFX(gcSmiIdtr)
global ASM_PFX(gcSmiGdtr)
@@ -369,9 +370,14 @@ ASM_PFX(PageFaultIdtHandlerSmmProfile): mov rsp, rbp
+; Check if mSetupDebugTrap is TRUE (non-zero)
+ cmp byte [dword ASM_PFX(mSetupDebugTrap)], 0
+ jz SkipSettingTF
+
; Enable TF bit after page fault handler runs
bts dword [rsp + 40], 8 ;RFLAGS
+SkipSettingTF:
pop rbp
add rsp, 16 ; skip INT# & ErrCode
iretq
|