diff options
| author | Eric Dong <eric.dong@intel.com> | 2018-08-30 13:57:58 +0800 |
|---|---|---|
| committer | Eric Dong <eric.dong@intel.com> | 2018-09-26 15:17:12 +0800 |
| commit | c4b073632d6fa2fd9079fb6d088738bb7d5c7f71 (patch) | |
| tree | db80e69f1090170529446b6ee3bb23c666f80a2f /UefiCpuPkg | |
| parent | 47f75d2169eca006d93216f14f86ded6470f9be2 (diff) | |
| download | edk2-c4b073632d6fa2fd9079fb6d088738bb7d5c7f71.tar.gz edk2-c4b073632d6fa2fd9079fb6d088738bb7d5c7f71.tar.bz2 edk2-c4b073632d6fa2fd9079fb6d088738bb7d5c7f71.zip | |
UefiCpuPkg/Include/Register/Msr/*.h: Add new MSR.
Changes includes:
1. Add new MSR: MSR_*_MSRUNCORE_RATIO_LIMIT
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Diffstat (limited to 'UefiCpuPkg')
| -rw-r--r-- | UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 54 | ||||
| -rw-r--r-- | UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h | 56 | ||||
| -rw-r--r-- | UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 56 |
3 files changed, 164 insertions, 2 deletions
diff --git a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h index 4e50f72008..a7a1967420 100644 --- a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h @@ -286,6 +286,60 @@ typedef union { /**
+ Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
+ fields represent the widest possible range of uncore frequencies. Writing to
+ these fields allows software to control the minimum and the maximum
+ frequency that hardware will select.
+
+ @param ECX MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x00000620)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT);
+ AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
+ @endcode
+**/
+#define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT 0x00000620
+
+/**
+ MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
+ /// LLC/Ring.
+ ///
+ UINT32 MAX_RATIO:7;
+ UINT32 Reserved2:1;
+ ///
+ /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
+ /// possible ratio of the LLC/Ring.
+ ///
+ UINT32 MIN_RATIO:7;
+ UINT32 Reserved3:17;
+ UINT32 Reserved4:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER;
+
+/**
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
Domains.".
diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h index a75bdb2e13..985183b320 100644 --- a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h @@ -846,7 +846,61 @@ typedef union { /**
- Package. Reserved (R/O) Reads return 0.
+ Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
+ fields represent the widest possible range of uncore frequencies. Writing to
+ these fields allows software to control the minimum and the maximum
+ frequency that hardware will select.
+
+ @param ECX MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT (0x00000620)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT);
+ AsmWriteMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
+ @endcode
+**/
+#define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT 0x00000620
+
+/**
+ MSR information returned for MSR index #MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
+ /// LLC/Ring.
+ ///
+ UINT32 MAX_RATIO:7;
+ UINT32 Reserved1:1;
+ ///
+ /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
+ /// possible ratio of the LLC/Ring.
+ ///
+ UINT32 MIN_RATIO:7;
+ UINT32 Reserved2:17;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER;
+
+/**
+ Package. Reserved (R/O) Reads return 0.
@param ECX MSR_HASWELL_E_PP0_ENERGY_STATUS (0x00000639)
@param EAX Lower 32-bits of MSR value.
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h index cf013ea887..6dc4ee999e 100644 --- a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h @@ -754,7 +754,61 @@ typedef union { /**
- Package. Reserved (R/O) Reads return 0.
+ Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
+ fields represent the widest possible range of uncore frequencies. Writing to
+ these fields allows software to control the minimum and the maximum
+ frequency that hardware will select.
+
+ @param ECX MSR_XEON_D_MSRUNCORE_RATIO_LIMIT (0x00000620)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT);
+ AsmWriteMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
+ @endcode
+**/
+#define MSR_XEON_D_MSRUNCORE_RATIO_LIMIT 0x00000620
+
+/**
+ MSR information returned for MSR index #MSR_XEON_D_MSRUNCORE_RATIO_LIMIT
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
+ /// LLC/Ring.
+ ///
+ UINT32 MAX_RATIO:7;
+ UINT32 Reserved1:1;
+ ///
+ /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
+ /// possible ratio of the LLC/Ring.
+ ///
+ UINT32 MIN_RATIO:7;
+ UINT32 Reserved2:17;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER;
+
+/**
+ Package. Reserved (R/O) Reads return 0.
@param ECX MSR_XEON_D_PP0_ENERGY_STATUS (0x00000639)
@param EAX Lower 32-bits of MSR value.
|