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| author | Liu, Zhiguang <Zhiguang.Liu@intel.com> | 2021-12-01 09:59:17 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-12-08 04:08:21 +0000 |
| commit | b2f7ee2dedb4def586969f7bfae6911b9f089a93 (patch) | |
| tree | 2b314531c3f43431a0a35403982ab8f78e1c1d35 /UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.inf | |
| parent | ca78281c2595a58dcb2e2cb20352914e2f6dafec (diff) | |
| download | edk2-b2f7ee2dedb4def586969f7bfae6911b9f089a93.tar.gz edk2-b2f7ee2dedb4def586969f7bfae6911b9f089a93.tar.bz2 edk2-b2f7ee2dedb4def586969f7bfae6911b9f089a93.zip | |
UefiPayloadPkg: Increase SystemMemoryUefiRegionSize from 32M to 64M
Current, the SystemMemoryUefiRegionSize is 32M, which means in universal
payload entry, we can at most use 32M heap.
However, this can't meet the memory requirment for 5 level page table.
In UefiPayloadPkg\UefiPayloadEntry\X64\VirtualMemory.c, we assume the
Physical Address at most has 52 bits. Using 1G table support, with 52 bits
Physical Address, to build page table, we need one page to hold 16 PML5
entries, each PML5 entry points to one page containing 512 PML4 entries.
One PML4 entry points to one page containing 512 PML3 entries. Each PML3
entries will point to 1G memory space. Totally 8209 pages are needed,
which is around 32M bytes.
Therefore, increase SystemMemoryUefiRegionSize from 32M to 64M to support
5 level page tables.
Reviewed-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Diffstat (limited to 'UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.inf')
0 files changed, 0 insertions, 0 deletions