diff options
| -rw-r--r-- | ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 9 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 9 |
2 files changed, 8 insertions, 10 deletions
diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S index 1adf960377..f744cd6738 100644 --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S @@ -13,6 +13,8 @@ .set DAIF_RD_FIQ_BIT, (1 << 6)
.set DAIF_RD_IRQ_BIT, (1 << 7)
+.set SCTLR_ELx_M_BIT_POS, (0)
+
ASM_FUNC(ArmReadMidr)
mrs x0, midr_el1 // Read from Main ID Register (MIDR)
ret
@@ -122,11 +124,16 @@ ASM_FUNC(ArmUpdateTranslationTableEntry) lsr x1, x1, #12
EL1_OR_EL2_OR_EL3(x0)
1: tlbi vaae1, x1 // TLB Invalidate VA , EL1
+ mrs x2, sctlr_el1
b 4f
2: tlbi vae2, x1 // TLB Invalidate VA , EL2
+ mrs x2, sctlr_el2
b 4f
3: tlbi vae3, x1 // TLB Invalidate VA , EL3
-4: dsb nsh
+ mrs x2, sctlr_el3
+4: tbnz x2, SCTLR_ELx_M_BIT_POS, 5f
+ dc ivac, x0 // invalidate in Dcache if MMU is still off
+5: dsb nsh
isb
ret
diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index e8f5c69e31..204e33c75f 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -699,15 +699,6 @@ ArmConfigureMmu ( ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64));
- // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs
- ArmDisableMmu ();
- ArmDisableDataCache ();
- ArmDisableInstructionCache ();
-
- // Make sure nothing sneaked into the cache
- ArmCleanInvalidateDataCache ();
- ArmInvalidateInstructionCache ();
-
TranslationTableAttribute = TT_ATTR_INDX_INVALID;
while (MemoryTable->Length != 0) {
|