diff options
Diffstat (limited to 'ArmPkg/Include/IndustryStandard')
| -rw-r--r-- | ArmPkg/Include/IndustryStandard/ArmCache.h | 83 | ||||
| -rw-r--r-- | ArmPkg/Include/IndustryStandard/ArmFfaSvc.h | 42 | ||||
| -rw-r--r-- | ArmPkg/Include/IndustryStandard/ArmMmSvc.h | 56 | ||||
| -rw-r--r-- | ArmPkg/Include/IndustryStandard/ArmStdSmc.h | 88 |
4 files changed, 134 insertions, 135 deletions
diff --git a/ArmPkg/Include/IndustryStandard/ArmCache.h b/ArmPkg/Include/IndustryStandard/ArmCache.h index f9de46b5bf..27a91fcda2 100644 --- a/ArmPkg/Include/IndustryStandard/ArmCache.h +++ b/ArmPkg/Include/IndustryStandard/ArmCache.h @@ -13,22 +13,21 @@ // The ARM Architecture Reference Manual for ARMv8-A defines up
// to 7 levels of cache, L1 through L7.
-#define MAX_ARM_CACHE_LEVEL 7
+#define MAX_ARM_CACHE_LEVEL 7
/// Defines the structure of the CSSELR (Cache Size Selection) register
typedef union {
struct {
- UINT32 InD :1; ///< Instruction not Data bit
- UINT32 Level :3; ///< Cache level (zero based)
- UINT32 TnD :1; ///< Allocation not Data bit
- UINT32 Reserved :27; ///< Reserved, RES0
- } Bits; ///< Bitfield definition of the register
- UINT32 Data; ///< The entire 32-bit value
+ UINT32 InD : 1; ///< Instruction not Data bit
+ UINT32 Level : 3; ///< Cache level (zero based)
+ UINT32 TnD : 1; ///< Allocation not Data bit
+ UINT32 Reserved : 27; ///< Reserved, RES0
+ } Bits; ///< Bitfield definition of the register
+ UINT32 Data; ///< The entire 32-bit value
} CSSELR_DATA;
/// The cache type values for the InD field of the CSSELR register
-typedef enum
-{
+typedef enum {
/// Select the data or unified cache
CsselrCacheTypeDataOrUnified = 0,
/// Select the instruction cache
@@ -39,35 +38,35 @@ typedef enum /// Defines the structure of the CCSIDR (Current Cache Size ID) register
typedef union {
struct {
- UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
- UINT64 Associativity :10; ///< Associativity - 1
- UINT64 NumSets :15; ///< Number of sets in the cache -1
- UINT64 Unknown :4; ///< Reserved, UNKNOWN
- UINT64 Reserved :32; ///< Reserved, RES0
+ UINT64 LineSize : 3; ///< Line size (Log2(Num bytes in cache) - 4)
+ UINT64 Associativity : 10; ///< Associativity - 1
+ UINT64 NumSets : 15; ///< Number of sets in the cache -1
+ UINT64 Unknown : 4; ///< Reserved, UNKNOWN
+ UINT64 Reserved : 32; ///< Reserved, RES0
} BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
struct {
- UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
- UINT64 Associativity :21; ///< Associativity - 1
- UINT64 Reserved1 :8; ///< Reserved, RES0
- UINT64 NumSets :24; ///< Number of sets in the cache -1
- UINT64 Reserved2 :8; ///< Reserved, RES0
+ UINT64 LineSize : 3; ///< Line size (Log2(Num bytes in cache) - 4)
+ UINT64 Associativity : 21; ///< Associativity - 1
+ UINT64 Reserved1 : 8; ///< Reserved, RES0
+ UINT64 NumSets : 24; ///< Number of sets in the cache -1
+ UINT64 Reserved2 : 8; ///< Reserved, RES0
} BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.
struct {
- UINT64 LineSize : 3;
- UINT64 Associativity : 21;
- UINT64 Reserved : 8;
- UINT64 Unallocated : 32;
+ UINT64 LineSize : 3;
+ UINT64 Associativity : 21;
+ UINT64 Reserved : 8;
+ UINT64 Unallocated : 32;
} BitsCcidxAA32;
- UINT64 Data; ///< The entire 64-bit value
+ UINT64 Data; ///< The entire 64-bit value
} CCSIDR_DATA;
/// Defines the structure of the AARCH32 CCSIDR2 register.
typedef union {
struct {
- UINT32 NumSets :24; ///< Number of sets in the cache - 1
- UINT32 Reserved :8; ///< Reserved, RES0
- } Bits; ///< Bitfield definition of the register
- UINT32 Data; ///< The entire 32-bit value
+ UINT32 NumSets : 24; ///< Number of sets in the cache - 1
+ UINT32 Reserved : 8; ///< Reserved, RES0
+ } Bits; ///< Bitfield definition of the register
+ UINT32 Data; ///< The entire 32-bit value
} CCSIDR2_DATA;
/** Defines the structure of the CLIDR (Cache Level ID) register.
@@ -77,19 +76,19 @@ typedef union { **/
typedef union {
struct {
- UINT32 Ctype1 : 3; ///< Level 1 cache type
- UINT32 Ctype2 : 3; ///< Level 2 cache type
- UINT32 Ctype3 : 3; ///< Level 3 cache type
- UINT32 Ctype4 : 3; ///< Level 4 cache type
- UINT32 Ctype5 : 3; ///< Level 5 cache type
- UINT32 Ctype6 : 3; ///< Level 6 cache type
- UINT32 Ctype7 : 3; ///< Level 7 cache type
- UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
- UINT32 LoC : 3; ///< Level of Coherency
- UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
- UINT32 Icb : 3; ///< Inner Cache Boundary
- } Bits; ///< Bitfield definition of the register
- UINT32 Data; ///< The entire 32-bit value
+ UINT32 Ctype1 : 3; ///< Level 1 cache type
+ UINT32 Ctype2 : 3; ///< Level 2 cache type
+ UINT32 Ctype3 : 3; ///< Level 3 cache type
+ UINT32 Ctype4 : 3; ///< Level 4 cache type
+ UINT32 Ctype5 : 3; ///< Level 5 cache type
+ UINT32 Ctype6 : 3; ///< Level 6 cache type
+ UINT32 Ctype7 : 3; ///< Level 7 cache type
+ UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
+ UINT32 LoC : 3; ///< Level of Coherency
+ UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
+ UINT32 Icb : 3; ///< Inner Cache Boundary
+ } Bits; ///< Bitfield definition of the register
+ UINT32 Data; ///< The entire 32-bit value
} CLIDR_DATA;
/// The cache types reported in the CLIDR register.
@@ -107,6 +106,6 @@ typedef enum { ClidrCacheTypeMax
} CLIDR_CACHE_TYPE;
-#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
+#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
#endif /* ARM_CACHE_H_ */
diff --git a/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h b/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h index ebcb54b28b..4126a4985b 100644 --- a/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h +++ b/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h @@ -16,34 +16,34 @@ #ifndef ARM_FFA_SVC_H_
#define ARM_FFA_SVC_H_
-#define ARM_SVC_ID_FFA_VERSION_AARCH32 0x84000063
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32 0x8400006F
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 0x84000070
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 0xC400006F
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC4000070
+#define ARM_SVC_ID_FFA_VERSION_AARCH32 0x84000063
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32 0x8400006F
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 0x84000070
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 0xC400006F
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC4000070
/* Generic IDs when using AArch32 or AArch64 execution state */
#ifdef MDE_CPU_AARCH64
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64
#endif
#ifdef MDE_CPU_ARM
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32
#endif
-#define SPM_MAJOR_VERSION_FFA 1
-#define SPM_MINOR_VERSION_FFA 0
+#define SPM_MAJOR_VERSION_FFA 1
+#define SPM_MINOR_VERSION_FFA 0
-#define ARM_FFA_SPM_RET_SUCCESS 0
-#define ARM_FFA_SPM_RET_NOT_SUPPORTED -1
-#define ARM_FFA_SPM_RET_INVALID_PARAMETERS -2
-#define ARM_FFA_SPM_RET_NO_MEMORY -3
-#define ARM_FFA_SPM_RET_BUSY -4
-#define ARM_FFA_SPM_RET_INTERRUPTED -5
-#define ARM_FFA_SPM_RET_DENIED -6
-#define ARM_FFA_SPM_RET_RETRY -7
-#define ARM_FFA_SPM_RET_ABORTED -8
+#define ARM_FFA_SPM_RET_SUCCESS 0
+#define ARM_FFA_SPM_RET_NOT_SUPPORTED -1
+#define ARM_FFA_SPM_RET_INVALID_PARAMETERS -2
+#define ARM_FFA_SPM_RET_NO_MEMORY -3
+#define ARM_FFA_SPM_RET_BUSY -4
+#define ARM_FFA_SPM_RET_INTERRUPTED -5
+#define ARM_FFA_SPM_RET_DENIED -6
+#define ARM_FFA_SPM_RET_RETRY -7
+#define ARM_FFA_SPM_RET_ABORTED -8
// For now, the destination id to be used in the FF-A calls
// is being hard-coded. Subsequently, support will be added
@@ -51,6 +51,6 @@ // This is the endpoint id used by the optee os's implementation
// of the spmc.
// https://github.com/OP-TEE/optee_os/blob/master/core/arch/arm/kernel/stmm_sp.c#L66
-#define ARM_FFA_DESTINATION_ENDPOINT_ID 3
+#define ARM_FFA_DESTINATION_ENDPOINT_ID 3
#endif // ARM_FFA_SVC_H_
diff --git a/ArmPkg/Include/IndustryStandard/ArmMmSvc.h b/ArmPkg/Include/IndustryStandard/ArmMmSvc.h index deb3bc99d2..11aa50e3ac 100644 --- a/ArmPkg/Include/IndustryStandard/ArmMmSvc.h +++ b/ArmPkg/Include/IndustryStandard/ArmMmSvc.h @@ -14,49 +14,49 @@ * delegated events and request the Secure partition manager to perform
* privileged operations on its behalf.
*/
-#define ARM_SVC_ID_SPM_VERSION_AARCH32 0x84000060
-#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 0x84000061
-#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 0x84000064
-#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 0x84000065
-#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 0xC4000061
-#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 0xC4000064
-#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 0xC4000065
+#define ARM_SVC_ID_SPM_VERSION_AARCH32 0x84000060
+#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 0x84000061
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 0x84000064
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 0x84000065
+#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 0xC4000061
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 0xC4000064
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 0xC4000065
/* Generic IDs when using AArch32 or AArch64 execution state */
#ifdef MDE_CPU_AARCH64
-#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64
-#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64
-#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64
+#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64
#endif
#ifdef MDE_CPU_ARM
-#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32
-#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32
-#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32
+#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32
#endif
#define SET_MEM_ATTR_DATA_PERM_MASK 0x3
-#define SET_MEM_ATTR_DATA_PERM_SHIFT 0
-#define SET_MEM_ATTR_DATA_PERM_NO_ACCESS 0
-#define SET_MEM_ATTR_DATA_PERM_RW 1
-#define SET_MEM_ATTR_DATA_PERM_RO 3
+#define SET_MEM_ATTR_DATA_PERM_SHIFT 0
+#define SET_MEM_ATTR_DATA_PERM_NO_ACCESS 0
+#define SET_MEM_ATTR_DATA_PERM_RW 1
+#define SET_MEM_ATTR_DATA_PERM_RO 3
#define SET_MEM_ATTR_CODE_PERM_MASK 0x1
-#define SET_MEM_ATTR_CODE_PERM_SHIFT 2
-#define SET_MEM_ATTR_CODE_PERM_X 0
-#define SET_MEM_ATTR_CODE_PERM_XN 1
+#define SET_MEM_ATTR_CODE_PERM_SHIFT 2
+#define SET_MEM_ATTR_CODE_PERM_X 0
+#define SET_MEM_ATTR_CODE_PERM_XN 1
#define SET_MEM_ATTR_MAKE_PERM_REQUEST(d_perm, c_perm) \
((((c_perm) & SET_MEM_ATTR_CODE_PERM_MASK) << SET_MEM_ATTR_CODE_PERM_SHIFT) | \
(( (d_perm) & SET_MEM_ATTR_DATA_PERM_MASK) << SET_MEM_ATTR_DATA_PERM_SHIFT))
/* MM SVC Return error codes */
-#define ARM_SVC_SPM_RET_SUCCESS 0
-#define ARM_SVC_SPM_RET_NOT_SUPPORTED -1
-#define ARM_SVC_SPM_RET_INVALID_PARAMS -2
-#define ARM_SVC_SPM_RET_DENIED -3
-#define ARM_SVC_SPM_RET_NO_MEMORY -5
-
-#define SPM_MAJOR_VERSION 0
-#define SPM_MINOR_VERSION 1
+#define ARM_SVC_SPM_RET_SUCCESS 0
+#define ARM_SVC_SPM_RET_NOT_SUPPORTED -1
+#define ARM_SVC_SPM_RET_INVALID_PARAMS -2
+#define ARM_SVC_SPM_RET_DENIED -3
+#define ARM_SVC_SPM_RET_NO_MEMORY -5
+
+#define SPM_MAJOR_VERSION 0
+#define SPM_MINOR_VERSION 1
#endif // ARM_MM_SVC_H_
diff --git a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h index 9116a291da..655edc21b2 100644 --- a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h +++ b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h @@ -17,64 +17,64 @@ * SMC function IDs for Standard Service queries
*/
-#define ARM_SMC_ID_STD_CALL_COUNT 0x8400ff00
-#define ARM_SMC_ID_STD_UID 0x8400ff01
+#define ARM_SMC_ID_STD_CALL_COUNT 0x8400ff00
+#define ARM_SMC_ID_STD_UID 0x8400ff01
/* 0x8400ff02 is reserved */
-#define ARM_SMC_ID_STD_REVISION 0x8400ff03
+#define ARM_SMC_ID_STD_REVISION 0x8400ff03
/*
* The 'Standard Service Call UID' is supposed to return the Standard
* Service UUID. This is a 128-bit value.
*/
-#define ARM_SMC_STD_UUID0 0x108d905b
-#define ARM_SMC_STD_UUID1 0x47e8f863
-#define ARM_SMC_STD_UUID2 0xfbc02dae
-#define ARM_SMC_STD_UUID3 0xe2f64156
+#define ARM_SMC_STD_UUID0 0x108d905b
+#define ARM_SMC_STD_UUID1 0x47e8f863
+#define ARM_SMC_STD_UUID2 0xfbc02dae
+#define ARM_SMC_STD_UUID3 0xe2f64156
/*
* ARM Standard Service Calls revision numbers
* The current revision is: 0.1
*/
-#define ARM_SMC_STD_REVISION_MAJOR 0x0
-#define ARM_SMC_STD_REVISION_MINOR 0x1
+#define ARM_SMC_STD_REVISION_MAJOR 0x0
+#define ARM_SMC_STD_REVISION_MINOR 0x1
/*
* Management Mode (MM) calls cover a subset of the Standard Service Call range.
* The list below is not exhaustive.
*/
-#define ARM_SMC_ID_MM_VERSION_AARCH32 0x84000040
-#define ARM_SMC_ID_MM_VERSION_AARCH64 0xC4000040
+#define ARM_SMC_ID_MM_VERSION_AARCH32 0x84000040
+#define ARM_SMC_ID_MM_VERSION_AARCH64 0xC4000040
// Request service from secure standalone MM environment
-#define ARM_SMC_ID_MM_COMMUNICATE_AARCH32 0x84000041
-#define ARM_SMC_ID_MM_COMMUNICATE_AARCH64 0xC4000041
+#define ARM_SMC_ID_MM_COMMUNICATE_AARCH32 0x84000041
+#define ARM_SMC_ID_MM_COMMUNICATE_AARCH64 0xC4000041
/* Generic ID when using AArch32 or AArch64 execution state */
#ifdef MDE_CPU_AARCH64
-#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH64
+#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH64
#endif
#ifdef MDE_CPU_ARM
-#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH32
+#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH32
#endif
/* MM return error codes */
-#define ARM_SMC_MM_RET_SUCCESS 0
-#define ARM_SMC_MM_RET_NOT_SUPPORTED -1
-#define ARM_SMC_MM_RET_INVALID_PARAMS -2
-#define ARM_SMC_MM_RET_DENIED -3
-#define ARM_SMC_MM_RET_NO_MEMORY -4
+#define ARM_SMC_MM_RET_SUCCESS 0
+#define ARM_SMC_MM_RET_NOT_SUPPORTED -1
+#define ARM_SMC_MM_RET_INVALID_PARAMS -2
+#define ARM_SMC_MM_RET_DENIED -3
+#define ARM_SMC_MM_RET_NO_MEMORY -4
// ARM Architecture Calls
-#define SMCCC_VERSION 0x80000000
-#define SMCCC_ARCH_FEATURES 0x80000001
-#define SMCCC_ARCH_SOC_ID 0x80000002
-#define SMCCC_ARCH_WORKAROUND_1 0x80008000
-#define SMCCC_ARCH_WORKAROUND_2 0x80007FFF
+#define SMCCC_VERSION 0x80000000
+#define SMCCC_ARCH_FEATURES 0x80000001
+#define SMCCC_ARCH_SOC_ID 0x80000002
+#define SMCCC_ARCH_WORKAROUND_1 0x80008000
+#define SMCCC_ARCH_WORKAROUND_2 0x80007FFF
#define SMC_ARCH_CALL_SUCCESS 0
-#define SMC_ARCH_CALL_NOT_SUPPORTED -1
-#define SMC_ARCH_CALL_NOT_REQUIRED -2
-#define SMC_ARCH_CALL_INVALID_PARAMETER -3
+#define SMC_ARCH_CALL_NOT_SUPPORTED -1
+#define SMC_ARCH_CALL_NOT_REQUIRED -2
+#define SMC_ARCH_CALL_INVALID_PARAMETER -3
/*
* Power State Coordination Interface (PSCI) calls cover a subset of the
@@ -101,15 +101,15 @@ ((ARM_SMC_PSCI_VERSION_MAJOR << 16) | ARM_SMC_PSCI_VERSION_MINOR)
/* PSCI return error codes */
-#define ARM_SMC_PSCI_RET_SUCCESS 0
-#define ARM_SMC_PSCI_RET_NOT_SUPPORTED -1
-#define ARM_SMC_PSCI_RET_INVALID_PARAMS -2
-#define ARM_SMC_PSCI_RET_DENIED -3
-#define ARM_SMC_PSCI_RET_ALREADY_ON -4
-#define ARM_SMC_PSCI_RET_ON_PENDING -5
-#define ARM_SMC_PSCI_RET_INTERN_FAIL -6
-#define ARM_SMC_PSCI_RET_NOT_PRESENT -7
-#define ARM_SMC_PSCI_RET_DISABLED -8
+#define ARM_SMC_PSCI_RET_SUCCESS 0
+#define ARM_SMC_PSCI_RET_NOT_SUPPORTED -1
+#define ARM_SMC_PSCI_RET_INVALID_PARAMS -2
+#define ARM_SMC_PSCI_RET_DENIED -3
+#define ARM_SMC_PSCI_RET_ALREADY_ON -4
+#define ARM_SMC_PSCI_RET_ON_PENDING -5
+#define ARM_SMC_PSCI_RET_INTERN_FAIL -6
+#define ARM_SMC_PSCI_RET_NOT_PRESENT -7
+#define ARM_SMC_PSCI_RET_DISABLED -8
#define ARM_SMC_PSCI_TARGET_CPU32(Aff2, Aff1, Aff0) \
((((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))
@@ -120,10 +120,10 @@ #define ARM_SMC_PSCI_TARGET_GET_AFF0(TargetId) ((TargetId) & 0xFF)
#define ARM_SMC_PSCI_TARGET_GET_AFF1(TargetId) (((TargetId) >> 8) & 0xFF)
-#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0 0
-#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1 1
-#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2 2
-#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3 3
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0 0
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1 1
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2 2
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3 3
#define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON 0
#define ARM_SMC_ID_PSCI_AFFINITY_INFO_OFF 1
@@ -132,9 +132,9 @@ /*
* SMC function IDs for Trusted OS Service queries
*/
-#define ARM_SMC_ID_TOS_CALL_COUNT 0xbf00ff00
-#define ARM_SMC_ID_TOS_UID 0xbf00ff01
+#define ARM_SMC_ID_TOS_CALL_COUNT 0xbf00ff00
+#define ARM_SMC_ID_TOS_UID 0xbf00ff01
/* 0xbf00ff02 is reserved */
-#define ARM_SMC_ID_TOS_REVISION 0xbf00ff03
+#define ARM_SMC_ID_TOS_REVISION 0xbf00ff03
#endif // ARM_STD_SMC_H_
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