diff options
Diffstat (limited to 'ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c')
| -rw-r--r-- | ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 331 |
1 files changed, 193 insertions, 138 deletions
diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 8c736d25bb..89da40fd8e 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -26,31 +26,32 @@ ArmMemoryAttributeToPageAttribute ( )
{
switch (Attributes) {
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:
- return TT_ATTR_INDX_MEMORY_WRITE_BACK;
-
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
- return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
-
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
- return TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
-
- // Uncached and device mappings are treated as outer shareable by default,
- case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
- return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
-
- default:
- ASSERT (0);
- case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
- if (ArmReadCurrentEL () == AARCH64_EL2)
- return TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;
- else
- return TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:
+ return TT_ATTR_INDX_MEMORY_WRITE_BACK;
+
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
+ return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
+
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
+ return TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
+
+ // Uncached and device mappings are treated as outer shareable by default,
+ case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
+ return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
+
+ default:
+ ASSERT (0);
+ case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
+ if (ArmReadCurrentEL () == AARCH64_EL2) {
+ return TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;
+ } else {
+ return TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;
+ }
}
}
@@ -61,7 +62,7 @@ ArmMemoryAttributeToPageAttribute ( STATIC
UINTN
GetRootTableEntryCount (
- IN UINTN T0SZ
+ IN UINTN T0SZ
)
{
return TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL;
@@ -70,7 +71,7 @@ GetRootTableEntryCount ( STATIC
UINTN
GetRootTableLevel (
- IN UINTN T0SZ
+ IN UINTN T0SZ
)
{
return (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;
@@ -79,10 +80,10 @@ GetRootTableLevel ( STATIC
VOID
ReplaceTableEntry (
- IN UINT64 *Entry,
- IN UINT64 Value,
- IN UINT64 RegionStart,
- IN BOOLEAN IsLiveBlockMapping
+ IN UINT64 *Entry,
+ IN UINT64 Value,
+ IN UINT64 RegionStart,
+ IN BOOLEAN IsLiveBlockMapping
)
{
if (!ArmMmuEnabled () || !IsLiveBlockMapping) {
@@ -100,19 +101,22 @@ FreePageTablesRecursive ( IN UINTN Level
)
{
- UINTN Index;
+ UINTN Index;
ASSERT (Level <= 3);
if (Level < 3) {
for (Index = 0; Index < TT_ENTRY_COUNT; Index++) {
if ((TranslationTable[Index] & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {
- FreePageTablesRecursive ((VOID *)(UINTN)(TranslationTable[Index] &
- TT_ADDRESS_MASK_BLOCK_ENTRY),
- Level + 1);
+ FreePageTablesRecursive (
+ (VOID *)(UINTN)(TranslationTable[Index] &
+ TT_ADDRESS_MASK_BLOCK_ENTRY),
+ Level + 1
+ );
}
}
}
+
FreePages (TranslationTable, 1);
}
@@ -126,6 +130,7 @@ IsBlockEntry ( if (Level == 3) {
return (Entry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY_LEVEL3;
}
+
return (Entry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY;
}
@@ -143,39 +148,48 @@ IsTableEntry ( //
return FALSE;
}
+
return (Entry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY;
}
STATIC
EFI_STATUS
UpdateRegionMappingRecursive (
- IN UINT64 RegionStart,
- IN UINT64 RegionEnd,
- IN UINT64 AttributeSetMask,
- IN UINT64 AttributeClearMask,
- IN UINT64 *PageTable,
- IN UINTN Level
+ IN UINT64 RegionStart,
+ IN UINT64 RegionEnd,
+ IN UINT64 AttributeSetMask,
+ IN UINT64 AttributeClearMask,
+ IN UINT64 *PageTable,
+ IN UINTN Level
)
{
- UINTN BlockShift;
- UINT64 BlockMask;
- UINT64 BlockEnd;
- UINT64 *Entry;
- UINT64 EntryValue;
- VOID *TranslationTable;
- EFI_STATUS Status;
+ UINTN BlockShift;
+ UINT64 BlockMask;
+ UINT64 BlockEnd;
+ UINT64 *Entry;
+ UINT64 EntryValue;
+ VOID *TranslationTable;
+ EFI_STATUS Status;
ASSERT (((RegionStart | RegionEnd) & EFI_PAGE_MASK) == 0);
BlockShift = (Level + 1) * BITS_PER_LEVEL + MIN_T0SZ;
- BlockMask = MAX_UINT64 >> BlockShift;
-
- DEBUG ((DEBUG_VERBOSE, "%a(%d): %llx - %llx set %lx clr %lx\n", __FUNCTION__,
- Level, RegionStart, RegionEnd, AttributeSetMask, AttributeClearMask));
-
- for (; RegionStart < RegionEnd; RegionStart = BlockEnd) {
+ BlockMask = MAX_UINT64 >> BlockShift;
+
+ DEBUG ((
+ DEBUG_VERBOSE,
+ "%a(%d): %llx - %llx set %lx clr %lx\n",
+ __FUNCTION__,
+ Level,
+ RegionStart,
+ RegionEnd,
+ AttributeSetMask,
+ AttributeClearMask
+ ));
+
+ for ( ; RegionStart < RegionEnd; RegionStart = BlockEnd) {
BlockEnd = MIN (RegionEnd, (RegionStart | BlockMask) + 1);
- Entry = &PageTable[(RegionStart >> (64 - BlockShift)) & (TT_ENTRY_COUNT - 1)];
+ Entry = &PageTable[(RegionStart >> (64 - BlockShift)) & (TT_ENTRY_COUNT - 1)];
//
// If RegionStart or BlockEnd is not aligned to the block size at this
@@ -187,8 +201,9 @@ UpdateRegionMappingRecursive ( // we cannot replace it with a block entry without potentially losing
// attribute information, so keep the table entry in that case.
//
- if (Level == 0 || ((RegionStart | BlockEnd) & BlockMask) != 0 ||
- (IsTableEntry (*Entry, Level) && AttributeClearMask != 0)) {
+ if ((Level == 0) || (((RegionStart | BlockEnd) & BlockMask) != 0) ||
+ (IsTableEntry (*Entry, Level) && (AttributeClearMask != 0)))
+ {
ASSERT (Level < 3);
if (!IsTableEntry (*Entry, Level)) {
@@ -216,9 +231,14 @@ UpdateRegionMappingRecursive ( // We are splitting an existing block entry, so we have to populate
// the new table with the attributes of the block entry it replaces.
//
- Status = UpdateRegionMappingRecursive (RegionStart & ~BlockMask,
- (RegionStart | BlockMask) + 1, *Entry & TT_ATTRIBUTES_MASK,
- 0, TranslationTable, Level + 1);
+ Status = UpdateRegionMappingRecursive (
+ RegionStart & ~BlockMask,
+ (RegionStart | BlockMask) + 1,
+ *Entry & TT_ATTRIBUTES_MASK,
+ 0,
+ TranslationTable,
+ Level + 1
+ );
if (EFI_ERROR (Status)) {
//
// The range we passed to UpdateRegionMappingRecursive () is block
@@ -236,9 +256,14 @@ UpdateRegionMappingRecursive ( //
// Recurse to the next level
//
- Status = UpdateRegionMappingRecursive (RegionStart, BlockEnd,
- AttributeSetMask, AttributeClearMask, TranslationTable,
- Level + 1);
+ Status = UpdateRegionMappingRecursive (
+ RegionStart,
+ BlockEnd,
+ AttributeSetMask,
+ AttributeClearMask,
+ TranslationTable,
+ Level + 1
+ );
if (EFI_ERROR (Status)) {
if (!IsTableEntry (*Entry, Level)) {
//
@@ -250,16 +275,21 @@ UpdateRegionMappingRecursive ( //
FreePageTablesRecursive (TranslationTable, Level + 1);
}
+
return Status;
}
if (!IsTableEntry (*Entry, Level)) {
EntryValue = (UINTN)TranslationTable | TT_TYPE_TABLE_ENTRY;
- ReplaceTableEntry (Entry, EntryValue, RegionStart,
- IsBlockEntry (*Entry, Level));
+ ReplaceTableEntry (
+ Entry,
+ EntryValue,
+ RegionStart,
+ IsBlockEntry (*Entry, Level)
+ );
}
} else {
- EntryValue = (*Entry & AttributeClearMask) | AttributeSetMask;
+ EntryValue = (*Entry & AttributeClearMask) | AttributeSetMask;
EntryValue |= RegionStart;
EntryValue |= (Level == 3) ? TT_TYPE_BLOCK_ENTRY_LEVEL3
: TT_TYPE_BLOCK_ENTRY;
@@ -280,6 +310,7 @@ UpdateRegionMappingRecursive ( }
}
}
+
return EFI_SUCCESS;
}
@@ -292,7 +323,7 @@ UpdateRegionMapping ( IN UINT64 AttributeClearMask
)
{
- UINTN T0SZ;
+ UINTN T0SZ;
if (((RegionStart | RegionLength) & EFI_PAGE_MASK) != 0) {
return EFI_INVALID_PARAMETER;
@@ -300,9 +331,14 @@ UpdateRegionMapping ( T0SZ = ArmGetTCR () & TCR_T0SZ_MASK;
- return UpdateRegionMappingRecursive (RegionStart, RegionStart + RegionLength,
- AttributeSetMask, AttributeClearMask, ArmGetTTBR0BaseAddress (),
- GetRootTableLevel (T0SZ));
+ return UpdateRegionMappingRecursive (
+ RegionStart,
+ RegionStart + RegionLength,
+ AttributeSetMask,
+ AttributeClearMask,
+ ArmGetTTBR0BaseAddress (),
+ GetRootTableLevel (T0SZ)
+ );
}
STATIC
@@ -323,31 +359,32 @@ FillTranslationTable ( STATIC
UINT64
GcdAttributeToPageAttribute (
- IN UINT64 GcdAttributes
+ IN UINT64 GcdAttributes
)
{
- UINT64 PageAttributes;
+ UINT64 PageAttributes;
switch (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) {
- case EFI_MEMORY_UC:
- PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;
- break;
- case EFI_MEMORY_WC:
- PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
- break;
- case EFI_MEMORY_WT:
- PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
- break;
- case EFI_MEMORY_WB:
- PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
- break;
- default:
- PageAttributes = TT_ATTR_INDX_MASK;
- break;
+ case EFI_MEMORY_UC:
+ PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;
+ break;
+ case EFI_MEMORY_WC:
+ PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
+ break;
+ case EFI_MEMORY_WT:
+ PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
+ break;
+ case EFI_MEMORY_WB:
+ PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
+ break;
+ default:
+ PageAttributes = TT_ATTR_INDX_MASK;
+ break;
}
- if ((GcdAttributes & EFI_MEMORY_XP) != 0 ||
- (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) == EFI_MEMORY_UC) {
+ if (((GcdAttributes & EFI_MEMORY_XP) != 0) ||
+ ((GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) == EFI_MEMORY_UC))
+ {
if (ArmReadCurrentEL () == AARCH64_EL2) {
PageAttributes |= TT_XN_MASK;
} else {
@@ -364,15 +401,15 @@ GcdAttributeToPageAttribute ( EFI_STATUS
ArmSetMemoryAttributes (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
)
{
- UINT64 PageAttributes;
- UINT64 PageAttributeMask;
+ UINT64 PageAttributes;
+ UINT64 PageAttributeMask;
- PageAttributes = GcdAttributeToPageAttribute (Attributes);
+ PageAttributes = GcdAttributeToPageAttribute (Attributes);
PageAttributeMask = 0;
if ((Attributes & EFI_MEMORY_CACHETYPE_MASK) == 0) {
@@ -380,22 +417,26 @@ ArmSetMemoryAttributes ( // No memory type was set in Attributes, so we are going to update the
// permissions only.
//
- PageAttributes &= TT_AP_MASK | TT_UXN_MASK | TT_PXN_MASK;
+ PageAttributes &= TT_AP_MASK | TT_UXN_MASK | TT_PXN_MASK;
PageAttributeMask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK |
TT_PXN_MASK | TT_XN_MASK);
}
- return UpdateRegionMapping (BaseAddress, Length, PageAttributes,
- PageAttributeMask);
+ return UpdateRegionMapping (
+ BaseAddress,
+ Length,
+ PageAttributes,
+ PageAttributeMask
+ );
}
STATIC
EFI_STATUS
SetMemoryRegionAttribute (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes,
- IN UINT64 BlockEntryMask
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes,
+ IN UINT64 BlockEntryMask
)
{
return UpdateRegionMapping (BaseAddress, Length, Attributes, BlockEntryMask);
@@ -403,11 +444,11 @@ SetMemoryRegionAttribute ( EFI_STATUS
ArmSetMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
- UINT64 Val;
+ UINT64 Val;
if (ArmReadCurrentEL () == AARCH64_EL1) {
Val = TT_PXN_MASK | TT_UXN_MASK;
@@ -419,16 +460,17 @@ ArmSetMemoryRegionNoExec ( BaseAddress,
Length,
Val,
- ~TT_ADDRESS_MASK_BLOCK_ENTRY);
+ ~TT_ADDRESS_MASK_BLOCK_ENTRY
+ );
}
EFI_STATUS
ArmClearMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
- UINT64 Mask;
+ UINT64 Mask;
// XN maps to UXN in the EL1&0 translation regime
Mask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_PXN_MASK | TT_XN_MASK);
@@ -437,50 +479,53 @@ ArmClearMemoryRegionNoExec ( BaseAddress,
Length,
0,
- Mask);
+ Mask
+ );
}
EFI_STATUS
ArmSetMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
return SetMemoryRegionAttribute (
BaseAddress,
Length,
TT_AP_RO_RO,
- ~TT_ADDRESS_MASK_BLOCK_ENTRY);
+ ~TT_ADDRESS_MASK_BLOCK_ENTRY
+ );
}
EFI_STATUS
ArmClearMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
return SetMemoryRegionAttribute (
BaseAddress,
Length,
TT_AP_RW_RW,
- ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK));
+ ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK)
+ );
}
EFI_STATUS
EFIAPI
ArmConfigureMmu (
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
- OUT VOID **TranslationTableBase OPTIONAL,
+ OUT VOID **TranslationTableBase OPTIONAL,
OUT UINTN *TranslationTableSize OPTIONAL
)
{
- VOID* TranslationTable;
- UINTN MaxAddressBits;
- UINT64 MaxAddress;
- UINTN T0SZ;
- UINTN RootTableEntryCount;
- UINT64 TCR;
- EFI_STATUS Status;
+ VOID *TranslationTable;
+ UINTN MaxAddressBits;
+ UINT64 MaxAddress;
+ UINTN T0SZ;
+ UINTN RootTableEntryCount;
+ UINT64 TCR;
+ EFI_STATUS Status;
if (MemoryTable == NULL) {
ASSERT (MemoryTable != NULL);
@@ -495,9 +540,9 @@ ArmConfigureMmu ( // use of 4 KB pages.
//
MaxAddressBits = MIN (ArmGetPhysicalAddressBits (), MAX_VA_BITS);
- MaxAddress = LShiftU64 (1ULL, MaxAddressBits) - 1;
+ MaxAddress = LShiftU64 (1ULL, MaxAddressBits) - 1;
- T0SZ = 64 - MaxAddressBits;
+ T0SZ = 64 - MaxAddressBits;
RootTableEntryCount = GetRootTableEntryCount (T0SZ);
//
@@ -506,7 +551,7 @@ ArmConfigureMmu ( // Ideally we will be running at EL2, but should support EL1 as well.
// UEFI should not run at EL3.
if (ArmReadCurrentEL () == AARCH64_EL2) {
- //Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2
+ // Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2
TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;
// Set the Physical Address Size using MaxAddress
@@ -523,9 +568,11 @@ ArmConfigureMmu ( } else if (MaxAddress < SIZE_256TB) {
TCR |= TCR_PS_256TB;
} else {
- DEBUG ((DEBUG_ERROR,
+ DEBUG ((
+ DEBUG_ERROR,
"ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n",
- MaxAddress));
+ MaxAddress
+ ));
ASSERT (0); // Bigger than 48-bit memory space are not supported
return EFI_UNSUPPORTED;
}
@@ -547,9 +594,11 @@ ArmConfigureMmu ( } else if (MaxAddress < SIZE_256TB) {
TCR |= TCR_IPS_256TB;
} else {
- DEBUG ((DEBUG_ERROR,
+ DEBUG ((
+ DEBUG_ERROR,
"ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n",
- MaxAddress));
+ MaxAddress
+ ));
ASSERT (0); // Bigger than 48-bit memory space are not supported
return EFI_UNSUPPORTED;
}
@@ -579,6 +628,7 @@ ArmConfigureMmu ( if (TranslationTable == NULL) {
return EFI_OUT_OF_RESOURCES;
}
+
//
// We set TTBR0 just after allocating the table to retrieve its location from
// the subsequent functions without needing to pass this value across the
@@ -599,8 +649,10 @@ ArmConfigureMmu ( // Make sure we are not inadvertently hitting in the caches
// when populating the page tables.
//
- InvalidateDataCacheRange (TranslationTable,
- RootTableEntryCount * sizeof (UINT64));
+ InvalidateDataCacheRange (
+ TranslationTable,
+ RootTableEntryCount * sizeof (UINT64)
+ );
ZeroMem (TranslationTable, RootTableEntryCount * sizeof (UINT64));
while (MemoryTable->Length != 0) {
@@ -608,6 +660,7 @@ ArmConfigureMmu ( if (EFI_ERROR (Status)) {
goto FreeTranslationTable;
}
+
MemoryTable++;
}
@@ -618,10 +671,10 @@ ArmConfigureMmu ( // EFI_MEMORY_WB ==> MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK
//
ArmSetMAIR (
- MAIR_ATTR (TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) |
+ MAIR_ATTR (TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) |
MAIR_ATTR (TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) |
MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) |
- MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)
+ MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)
);
ArmDisableAlignmentCheck ();
@@ -643,14 +696,16 @@ ArmMmuBaseLibConstructor ( VOID
)
{
- extern UINT32 ArmReplaceLiveTranslationEntrySize;
+ extern UINT32 ArmReplaceLiveTranslationEntrySize;
//
// The ArmReplaceLiveTranslationEntry () helper function may be invoked
// with the MMU off so we have to ensure that it gets cleaned to the PoC
//
- WriteBackDataCacheRange ((VOID *)(UINTN)ArmReplaceLiveTranslationEntry,
- ArmReplaceLiveTranslationEntrySize);
+ WriteBackDataCacheRange (
+ (VOID *)(UINTN)ArmReplaceLiveTranslationEntry,
+ ArmReplaceLiveTranslationEntrySize
+ );
return RETURN_SUCCESS;
}
|