diff options
Diffstat (limited to 'IntelFsp2Pkg')
| -rw-r--r-- | IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | 3 | ||||
| -rw-r--r-- | IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 52 | ||||
| -rw-r--r-- | IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm | 28 | ||||
| -rw-r--r-- | IntelFsp2Pkg/FspSecCore/SecMain.c | 76 | ||||
| -rw-r--r-- | IntelFsp2Pkg/FspSecCore/SecMain.h | 13 | ||||
| -rw-r--r-- | IntelFsp2Pkg/IntelFsp2Pkg.dec | 4 |
6 files changed, 157 insertions, 19 deletions
diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf index dafe6f5993..0024254e0e 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf @@ -1,7 +1,7 @@ ## @file
# Sec Core for FSP
#
-# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -38,6 +38,7 @@ Ia32/FspApiEntryM.nasm
Ia32/FspApiEntryCommon.nasm
Ia32/FspHelper.nasm
+ Ia32/ReadEsp.nasm
[Binaries.Ia32]
RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm index 9c9a84db0a..916ad4ff0d 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm @@ -1,7 +1,7 @@ ;; @file
; Provide FSP API entry points.
;
-; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -19,6 +19,7 @@ extern ASM_PFX(PcdGet32(PcdTemporaryRamBase))
extern ASM_PFX(PcdGet32(PcdTemporaryRamSize))
extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
+extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
struc FSPM_UPD_COMMON
; FSP_UPD_HEADER {
@@ -128,15 +129,55 @@ ASM_PFX(FspApiCommonContinue): add edx, [eax + FSP_HEADER_CFGREG_OFFSET]
pop eax
- FspStackSetup:
+FspStackSetup:
+ ;
+ ; StackBase = temp memory base, StackSize = temp memory size
+ ;
mov edi, [edx + FSPM_UPD_COMMON.StackBase]
mov ecx, [edx + FSPM_UPD_COMMON.StackSize]
+
+ ;
+ ; Keep using bootloader stack if heap size % is 0
+ ;
+ mov bl, BYTE [ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))]
+ cmp bl, 0
+ jz SkipStackSwitch
+
+ ;
+ ; Set up a dedicated temp ram stack for FSP if FSP heap size % doesn't equal 0
+ ;
add edi, ecx
;
- ; Setup new FSP stack
+ ; Switch to new FSP stack
;
- xchg edi, esp ; Exchange edi and esp, edi will be assigned to the current esp pointer and esp will be Stack base + Stack size
- mov ebx, esp ; Put Stack base + Stack size in ebx
+ xchg edi, esp ; Exchange edi and esp, edi will be assigned to the current esp pointer and esp will be Stack base + Stack size
+
+SkipStackSwitch:
+ ;
+ ; If heap size % is 0:
+ ; EDI is FSPM_UPD_COMMON.StackBase and will hold ESP later (boot loader stack pointer)
+ ; ECX is FSPM_UPD_COMMON.StackSize
+ ; ESP is boot loader stack pointer (no stack switch)
+ ; BL is 0 to indicate no stack switch (EBX will hold FSPM_UPD_COMMON.StackBase later)
+ ;
+ ; If heap size % is not 0
+ ; EDI is boot loader stack pointer
+ ; ECX is FSPM_UPD_COMMON.StackSize
+ ; ESP is new stack (FSPM_UPD_COMMON.StackBase + FSPM_UPD_COMMON.StackSize)
+ ; BL is NOT 0 to indicate stack has switched
+ ;
+ cmp bl, 0
+ jnz StackHasBeenSwitched
+
+ mov ebx, edi ; Put FSPM_UPD_COMMON.StackBase to ebx as temp memory base
+ mov edi, esp ; Put boot loader stack pointer to edi
+ jmp StackSetupDone
+
+StackHasBeenSwitched:
+ mov ebx, esp ; Put Stack base + Stack size in ebx
+ sub ebx, ecx ; Stack base + Stack size - Stack size as temp memory base
+
+StackSetupDone:
;
; Pass the API Idx to SecStartup
@@ -170,7 +211,6 @@ ASM_PFX(FspApiCommonContinue): ;
; Pass stack base and size into the PEI Core
;
- sub ebx, ecx ; Stack base + Stack size - Stack size
push ebx
push ecx
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm new file mode 100644 index 0000000000..ca29f0529c --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm @@ -0,0 +1,28 @@ +;; @file
+; Provide read ESP function
+;
+; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT32
+; EFIAPI
+; AsmReadEsp (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadEsp)
+ASM_PFX(AsmReadEsp):
+ mov eax, esp
+ ret
+
diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c b/IntelFsp2Pkg/FspSecCore/SecMain.c index 70460a3c8b..c7caa3e7f9 100644 --- a/IntelFsp2Pkg/FspSecCore/SecMain.c +++ b/IntelFsp2Pkg/FspSecCore/SecMain.c @@ -1,6 +1,6 @@ /** @file
- Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -83,7 +83,29 @@ SecStartup ( //
InitializeFloatingPointUnits ();
+ //
+ // Scenario 1 memory map when running on bootloader stack
+ //
+ // |-------------------|---->
+ // |Idt Table |
+ // |-------------------|
+ // |PeiService Pointer |
+ // |-------------------|
+ // | |
+ // | |
+ // | Heap |
+ // | |
+ // | |
+ // |-------------------|----> TempRamBase
+ //
+ //
+ // |-------------------|
+ // |Bootloader stack |----> somewhere in memory, FSP will share this stack.
+ // |-------------------|
+ //
+ // Scenario 2 memory map when running FSP on a separate stack
+ //
// |-------------------|---->
// |Idt Table |
// |-------------------|
@@ -135,11 +157,19 @@ SecStartup ( SecCoreData.BootFirmwareVolumeSize = (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *)BootFirmwareVolume)->FvLength;
SecCoreData.TemporaryRamBase = (VOID*)(UINTN) TempRamBase;
- SecCoreData.TemporaryRamSize = SizeOfRam;
- SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
- SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize * PcdGet8 (PcdFspHeapSizePercentage) / 100;
- SecCoreData.StackBase = (VOID*)(UINTN)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);
- SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;
+ if (PcdGet8 (PcdFspHeapSizePercentage) == 0) {
+ SecCoreData.TemporaryRamSize = SizeOfRam; // stack size that is going to be copied to the permanent memory
+ SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
+ SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize;
+ SecCoreData.StackBase = (VOID *)GetFspEntryStack(); // Share the same boot loader stack
+ SecCoreData.StackSize = 0;
+ } else {
+ SecCoreData.TemporaryRamSize = SizeOfRam;
+ SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
+ SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize * PcdGet8 (PcdFspHeapSizePercentage) / 100;
+ SecCoreData.StackBase = (VOID*)(UINTN)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);
+ SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;
+ }
DEBUG ((DEBUG_INFO, "Fsp BootFirmwareVolumeBase - 0x%x\n", SecCoreData.BootFirmwareVolumeBase));
DEBUG ((DEBUG_INFO, "Fsp BootFirmwareVolumeSize - 0x%x\n", SecCoreData.BootFirmwareVolumeSize));
@@ -194,15 +224,37 @@ SecTemporaryRamSupport ( UINTN HeapSize;
UINTN StackSize;
- HeapSize = CopySize * PcdGet8 (PcdFspHeapSizePercentage) / 100 ;
- StackSize = CopySize - HeapSize;
+ UINTN CurrentStack;
+ UINTN FspStackBase;
+
+ if (PcdGet8 (PcdFspHeapSizePercentage) == 0) {
+
+ CurrentStack = AsmReadEsp();
+ FspStackBase = (UINTN)GetFspEntryStack();
- OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;
- NewHeap = (VOID*)((UINTN)PermanentMemoryBase + StackSize);
+ StackSize = FspStackBase - CurrentStack;
+ HeapSize = CopySize;
- OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize);
- NewStack = (VOID*)(UINTN)PermanentMemoryBase;
+ OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;
+ NewHeap = (VOID*)((UINTN)PermanentMemoryBase);
+ OldStack = (VOID*)CurrentStack;
+ //
+ //The old stack is copied at the end of the stack region because stack grows down.
+ //
+ NewStack = (VOID*)((UINTN)PermanentMemoryBase - StackSize);
+
+ } else {
+ HeapSize = CopySize * PcdGet8 (PcdFspHeapSizePercentage) / 100 ;
+ StackSize = CopySize - HeapSize;
+
+ OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;
+ NewHeap = (VOID*)((UINTN)PermanentMemoryBase + StackSize);
+
+ OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize);
+ NewStack = (VOID*)(UINTN)PermanentMemoryBase;
+
+ }
//
// Migrate Heap
//
diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.h b/IntelFsp2Pkg/FspSecCore/SecMain.h index 19ac2fbfc1..d8fc00b714 100644 --- a/IntelFsp2Pkg/FspSecCore/SecMain.h +++ b/IntelFsp2Pkg/FspSecCore/SecMain.h @@ -135,4 +135,17 @@ ProcessLibraryConstructorList ( VOID
);
+/**
+
+ Return value of esp.
+
+ @return value of esp.
+
+**/
+UINT32
+EFIAPI
+AsmReadEsp (
+ VOID
+ );
+
#endif
diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec index 64a31b3505..d4c6d221a1 100644 --- a/IntelFsp2Pkg/IntelFsp2Pkg.dec +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec @@ -86,8 +86,12 @@ gIntelFsp2PkgTokenSpaceGuid.PcdFspBootFirmwareVolumeBase|0xFFF80000|UINT32|0x10000003
gIntelFsp2PkgTokenSpaceGuid.PcdFspHeaderSpecVersion | 0x20| UINT8|0x00000002
+ #
# x % of FSP temporary memory will be used for heap
# (100 - x) % of FSP temporary memory will be used for stack
+ # 0 means FSP will share the stack with boot loader and FSP temporary memory is heap
+ # Note: This mode assumes boot loader stack is large enough for FSP to use.
+ #
gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage | 50| UINT8|0x10000004
#
# Maximal Interrupt supported in IDT table.
|